| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix padding, remove CIs from undriven_bits before erasing undriven POs | Eddie Hung | 2019-05-26 | 1 | -14/+8 |
| * | Fix "a" extension | Eddie Hung | 2019-05-26 | 1 | -8/+18 |
| * | Fix "write_xaiger", and to write each box contents into holes | Eddie Hung | 2019-05-25 | 1 | -39/+62 |
| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-25 | 2 | -7/+27 |
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| | * | Fix handling of offset and upto module ports in write_blif, fixes #1040 | Clifford Wolf | 2019-05-25 | 1 | -6/+20 |
| | * | Add proper error message for btor recursion_guard | Clifford Wolf | 2019-05-24 | 1 | -1/+7 |
| * | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -3/+7 |
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| | * | Fix static shift operands, neg result type, minor formatting | Jim Lawson | 2019-05-21 | 1 | -3/+7 |
| * | | Pad all boxes so that all input/output connections specified | Eddie Hung | 2019-05-21 | 1 | -22/+67 |
| * | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 3 | -11/+129 |
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| | * | Merge pull request #991 from kristofferkoch/gcc9-warnings | Clifford Wolf | 2019-05-08 | 1 | -1/+2 |
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| | | * | Fix all warnings that occurred when compiling with gcc9 | Kristoffer Ellersgaard Koch | 2019-05-08 | 1 | -1/+2 |
| | * | | Fix handling of partial init attributes in write_verilog, fixes #997 | Clifford Wolf | 2019-05-07 | 1 | -1/+2 |
| | * | | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 1 | -1/+4 |
| | * | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -15/+71 |
| | * | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -25/+62 |
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| | * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | * | | Add $specify2/$specify3 support to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+47 |
| | * | | Add support for $assert/$assume/$cover to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+10 |
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-02 | 1 | -25/+62 |
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| | * | | Re-indent firrtl.cc:struct memory - no functional change. | Jim Lawson | 2019-05-01 | 1 | -25/+25 |
| | * | | Fix #938 - Crash occurs in case when use write_firrtl command | Jim Lawson | 2019-05-01 | 1 | -4/+41 |
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| * | | Remove topo sort no-loop assertion, with test | Eddie Hung | 2019-04-24 | 1 | -13/+0 |
| * | | Fix abc9 with (* keep *) wires | Eddie Hung | 2019-04-23 | 1 | -6/+14 |
| * | | Temporarily remove 'r' extension | Eddie Hung | 2019-04-22 | 1 | -77/+7 |
| * | | Allow POs to be PIs in XAIG | Eddie Hung | 2019-04-22 | 1 | -7/+4 |
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -0/+8 |
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| | * | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 |
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 1 | -1/+1 |
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| | * | Merge pull request #943 from YosysHQ/clifford/whitebox | Clifford Wolf | 2019-04-20 | 8 | -12/+12 |
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| | | * | Revert "write_json to not write contents (cells/wires) of whiteboxes" | Eddie Hung | 2019-04-18 | 1 | -59/+56 |
| | | * | write_json to not write contents (cells/wires) of whiteboxes | Eddie Hung | 2019-04-18 | 1 | -56/+59 |
| | * | | Change "ne" to "neq" in btor2 output | Clifford Wolf | 2019-04-19 | 1 | -1/+1 |
| * | | | Fixes for simple_abc9 tests | Eddie Hung | 2019-04-19 | 1 | -4/+8 |
| * | | | Do not assume inst_module is always present | Eddie Hung | 2019-04-19 | 1 | -12/+9 |
| * | | | ignore_boxes -> holes_mode | Eddie Hung | 2019-04-19 | 1 | -6/+5 |
| * | | | Add flop support for write_xaiger | Eddie Hung | 2019-04-18 | 1 | -11/+83 |
| * | | | Spelling | Eddie Hung | 2019-04-18 | 1 | -1/+1 |
| * | | | Use new -wb flag for ABC flow | Eddie Hung | 2019-04-18 | 1 | -29/+31 |
| * | | | write_json to not write contents (cells/wires) of whiteboxes | Eddie Hung | 2019-04-18 | 1 | -56/+59 |
| * | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 8 | -12/+12 |
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| | * | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 8 | -12/+12 |
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| * | | Fix $anyseq warning and cleanup | Eddie Hung | 2019-04-17 | 1 | -16/+7 |
| * | | Cope with inout ports | Eddie Hung | 2019-04-17 | 1 | -1/+15 |
| * | | Stop topological sort at abc_flop_q | Eddie Hung | 2019-04-17 | 1 | -7/+13 |
| * | | Remove init* from xaiger, also topo-sort cells for box flow | Eddie Hung | 2019-04-17 | 1 | -95/+157 |
| * | | Optimise | Eddie Hung | 2019-04-16 | 1 | -4/+3 |
| * | | CIs before PIs; also sort each cell's connections before iterating | Eddie Hung | 2019-04-16 | 1 | -5/+7 |
| * | | Port from xc7mux branch | Eddie Hung | 2019-04-16 | 1 | -37/+109 |
| * | | Output __const0__ and __const1__ CIs | Eddie Hung | 2019-04-12 | 1 | -7/+10 |
