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* Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-201-42/+0
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| * Compute abc_scc_break and move CI/CO outside of each abc9Eddie Hung2019-08-161-42/+0
* | Fix various NDEBUG compiler warnings, closes #1255Clifford Wolf2019-08-131-1/+1
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* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-109-33/+33
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| * substr() -> compare()Eddie Hung2019-08-075-6/+6
| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-074-12/+12
| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-106/+240
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| * | Use IdString::begins_with()Eddie Hung2019-08-061-2/+2
| * | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-061-5/+5
| * | Use State::S{0,1}Eddie Hung2019-08-063-6/+6
| * | Make liberal use of IdString.in()Eddie Hung2019-08-062-2/+2
* | | Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cellClifford Wolf2019-08-101-1/+1
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| * \ \ Merge branch 'master' into firrtl_err_on_unsupported_cellJim Lawson2019-08-079-116/+287
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| * | | Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ...Jim Lawson2019-07-241-1/+1
* | | | Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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* | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-071-93/+203
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| * | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...Jim Lawson2019-07-311-93/+203
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* | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-071-13/+37
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| * | Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
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* | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-066-3/+40
* | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-1/+1
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| * | Visual Studio build fixMiodrag Milanovic2019-07-311-1/+1
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* / Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-6/+6
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* Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
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| * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
* | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
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* smt: handle failure of setrlimit syscallN. Engelhardt2019-07-151-1/+5
* Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
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| * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
* | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-positionClifford Wolf2019-07-091-3/+2
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| * | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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* | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscoreEddie Hung2019-07-091-4/+6
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| * Rename __builtin_bswap32 -> bswap32Eddie Hung2019-07-091-4/+6
* | verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
* | verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
* | Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-0/+5
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* write_xaiger to treat unknown cell connections as keep-sEddie Hung2019-07-021-6/+14
* Add generic __builtin_bswap32 functionEddie Hung2019-06-281-0/+15
* Also fix write_aiger for UBEddie Hung2019-06-281-26/+26
* Fix more potential for undefined behaviour due to container invalidationEddie Hung2019-06-281-6/+10
* Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-42/+40
* Merge origin/masterEddie Hung2019-06-272-4/+31
* Improve debugging message for comb loopsEddie Hung2019-06-261-4/+6
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-241-0/+4
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| * Fix json formattingMiodrag Milanovic2019-06-211-1/+1
| * Add upto and offset to JSON portsMiodrag Milanovic2019-06-211-0/+4
* | Carry in/out box ordering now move to end, not swap with endEddie Hung2019-06-221-26/+34
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-0/+4
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| * Added JSON upto and offsetClifford Wolf2019-06-211-0/+4
| * Fix gcc invalidation behaviour for write_aigerEddie Hung2019-06-201-1/+2