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Commit message (
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Author
Age
Files
Lines
*
rtlil: Dump empty connections when whole module is selected.
Marcelina Kościelnicka
2021-12-12
1
-2
/
+2
*
write_verilog: dump zero width sigspecs correctly.
whitequark
2021-12-11
1
-1
/
+2
*
sta: very crude static timing analysis pass
Lofty
2021-11-25
1
-15
/
+16
*
Give initial wire unique ID, fixes #2914
Miodrag Milanovic
2021-11-17
1
-4
/
+6
*
Split module ports, 20 per line
Miodrag Milanovic
2021-10-09
1
-0
/
+2
*
Hook up $aldff support in various passes.
Marcelina Kościelnicka
2021-10-02
4
-4
/
+19
*
kernel/ff: Refactor FfData to enable FFs with async load.
Marcelina Kościelnicka
2021-10-02
1
-43
/
+70
*
Add optimization to rtlil back-end for all-x parameter values
Claire Xenia Wolf
2021-09-27
1
-9
/
+13
*
Fix protobuf backend build dependencies
the6p4c
2021-09-17
1
-0
/
+2
*
yosys-smtbmc: Fix reused loop variable.
Marcelina Kościelnicka
2021-09-10
1
-4
/
+4
*
kernel/mem: Introduce transparency masks.
Marcelina Kościelnicka
2021-08-11
2
-27
/
+30
*
backend/verilog: Add alternate mode for transparent read port output.
Marcelina Kościelnicka
2021-08-01
1
-1
/
+71
*
backends/verilog: Support meminit with mask.
Marcelina Kościelnicka
2021-07-28
1
-3
/
+18
*
Merge pull request #2885 from whitequark/cxxrtl-fix-2883
whitequark
2021-07-20
1
-2
/
+8
|
\
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*
cxxrtl: treat wires with multiple defs as not inlinable.
whitequark
2021-07-20
1
-2
/
+8
*
|
cxxrtl: treat assignable internal wires used only for debug as locals.
whitequark
2021-07-20
1
-10
/
+12
|
/
*
cxxrtl: escape colon in variable names in VCD writer.
whitequark
2021-07-19
1
-1
/
+14
*
cxxrtl: add debug_item::{get,set}.
whitequark
2021-07-18
1
-0
/
+16
*
cxxrtl: treat internal wires used only for debug as constants.
whitequark
2021-07-17
1
-0
/
+6
*
Merge pull request #2874 from whitequark/cxxrtl-fix-2589
whitequark
2021-07-16
1
-9
/
+6
|
\
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*
cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.
whitequark
2021-07-16
1
-9
/
+6
*
|
Merge pull request #2873 from whitequark/cxxrtl-fix-2500
whitequark
2021-07-16
1
-3
/
+3
|
\
\
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*
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cxxrtl: emit debug items for unused public wires.
whitequark
2021-07-16
1
-3
/
+3
|
|
/
*
/
cxxrtl: don't expect user cell inputs to be wires.
whitequark
2021-07-16
1
-2
/
+2
|
/
*
cxxrtl: don't mark buffered internal wires as UNUSED for debug.
whitequark
2021-07-16
1
-1
/
+1
*
cxxrtl: mark dead local wires as unused even with inlining disabled.
whitequark
2021-07-15
1
-4
/
+6
*
kernel/mem: Add a coalesce_inits helper.
Marcelina Kościelnicka
2021-07-13
1
-1
/
+5
*
Add support for the Bitwuzla solver
GCHQDeveloper560
2021-07-12
1
-5
/
+5
*
cxxrtl: Support memory writes in processes.
Marcelina Kościelnicka
2021-07-12
1
-6
/
+55
*
cxxrtl: Add support for memory read port reset.
Marcelina Kościelnicka
2021-07-12
1
-1
/
+41
*
cxxrtl: Add support for mem read port initial data.
Marcelina Kościelnicka
2021-07-12
1
-4
/
+22
*
cxxrtl: Convert to Mem helpers.
Marcelina Kościelnicka
2021-07-12
1
-206
/
+276
*
Intersynth URL
Claire Xenia Wolf
2021-06-09
1
-1
/
+1
*
Fixing old e-mail addresses and deadnames
Claire Xenia Wolf
2021-06-08
19
-20
/
+20
*
Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
Marcelina Kościelnicka
2021-05-28
3
-19
/
+6
*
backends/verilog: Add support for memory read port reset and init value.
Marcelina Kościelnicka
2021-05-27
1
-9
/
+81
*
backends/verilog: Add wide port support.
Marcelina Kościelnicka
2021-05-27
1
-43
/
+88
*
backends/verilog: Try to preserve mem write port priorities.
Marcelina Kościelnicka
2021-05-26
1
-32
/
+84
*
Reject wide ports in some passes that will never support them.
Marcelina Kościelnicka
2021-05-25
3
-2
/
+21
*
backend/firrtl: Convert to use Mem helpers.
Marcelina Kościelnicka
2021-05-24
1
-264
/
+88
*
btor: Use is_mem_cell in one more place.
Marcelina Kościelnicka
2021-05-23
1
-1
/
+1
*
kernel/rtlil: Extract some helpers for checking memory cell types.
Marcelina Kościelnicka
2021-05-22
3
-4
/
+4
*
abc9: fix SCC issues (#2694)
Eddie Hung
2021-03-29
1
-5
/
+4
*
rtlil: Fix process memwr roundtrip.
Marcelina Kościelnicka
2021-03-23
1
-1
/
+1
*
json: Improve the "processes in module" message a bit.
Marcelina Kościelnicka
2021-03-23
1
-1
/
+1
*
json: Add support for memories.
Marcelina Kościelnicka
2021-03-15
1
-0
/
+42
*
Merge pull request #2642 from whitequark/cxxrtl-noproc-fixes
whitequark
2021-03-11
1
-17
/
+29
|
\
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*
cxxrtl: don't assert on edge sync rules tied to a constant.
whitequark
2021-03-07
1
-0
/
+4
|
*
cxxrtl: allow `always` sync rules in debug_eval.
whitequark
2021-03-07
1
-17
/
+25
*
|
Replace assert in xaiger with more useful error message
Dan Ravensloft
2021-03-10
1
-1
/
+2
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