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authorwhitequark <whitequark@whitequark.org>2021-03-07 14:29:30 +0000
committerwhitequark <whitequark@whitequark.org>2021-03-07 14:29:30 +0000
commitab76d9cec5ba38539f1578a78f3c810a659ea092 (patch)
treeeb3c237e7119053063900bdf531e5aeb8dd04312 /backends
parentd1de08e38a31c312cb0bd23e7376e80461bdcb22 (diff)
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cxxrtl: don't assert on edge sync rules tied to a constant.
These are commonly the result of tying an async reset to an inactive level.
Diffstat (limited to 'backends')
-rw-r--r--backends/cxxrtl/cxxrtl_backend.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index b6cc4bb6d..0071bda7f 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1518,6 +1518,8 @@ struct CxxrtlWorker {
if (!sync->signal.empty()) {
sync_bit = sync->signal[0];
sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
+ if (!sync_bit.is_wire())
+ continue; // a clock, or more commonly a reset, can be tied to a constant driver
}
pool<std::string> events;
@@ -2285,6 +2287,8 @@ struct CxxrtlWorker {
void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
{
signal = sigmap(signal);
+ if (signal.is_fully_const())
+ return; // a clock, or more commonly a reset, can be tied to a constant driver
log_assert(is_valid_clock(signal));
log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);