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| author | Eddie Hung <eddie@fpgeh.com> | 2021-03-29 22:01:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-29 22:01:57 -0700 |
| commit | 55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8 (patch) | |
| tree | ab4ab932ea29088baafcf3c71d6c5854403528d6 /backends | |
| parent | 687f381b6985d9dda7e11535628e2fafff267af5 (diff) | |
| download | yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.tar.gz yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.tar.bz2 yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.zip | |
abc9: fix SCC issues (#2694)
* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7ed8ff1cf..65ccc748f 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -156,7 +156,7 @@ struct XAigerWriter // promote keep wires for (auto wire : module->wires()) - if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep)) + if (wire->get_bool_attribute(ID::keep)) sigmap.add(wire); for (auto wire : module->wires()) { @@ -177,11 +177,10 @@ struct XAigerWriter undriven_bits.insert(bit); unused_bits.insert(bit); - bool keep = wire->get_bool_attribute(ID::abc9_keep); - if (wire->port_input || keep) + if (wire->port_input) input_bits.insert(bit); - keep = keep || wire->get_bool_attribute(ID::keep); + bool keep = wire->get_bool_attribute(ID::keep); if (wire->port_output || keep) { if (bit != wirebit) alias_map[wirebit] = bit; @@ -433,7 +432,7 @@ struct XAigerWriter if (bit == State::Sx) continue; if (aig_map.count(bit)) - log_error("Visited AIG node more than once; this could be a combinatorial loop that has not been broken - see Yosys bug 2530\n"); + log_error("Visited AIG node more than once; this could be a combinatorial loop that has not been broken\n"); aig_map[bit] = 2*aig_m; } |