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Author
Age
Files
Lines
*
Removed unused variables, functions.
Jim Lawson
2019-02-15
1
-20
/
+0
*
Update cells supported for verilog to FIRRTL conversion.
Jim Lawson
2019-02-15
1
-48
/
+225
*
Merge pull request #802 from whitequark/write_verilog_async_mem_ports
Clifford Wolf
2019-02-12
1
-38
/
+41
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write_verilog: correctly emit asynchronous transparent ports.
whitequark
2019-01-29
1
-38
/
+41
*
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Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...
Clifford Wolf
2019-02-06
1
-1
/
+1
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*
Merge pull request #800 from whitequark/write_verilog_tribuf
Clifford Wolf
2019-01-27
1
-0
/
+12
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write_verilog: write $tribuf cell as ternary.
whitequark
2019-01-27
1
-0
/
+12
*
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write_verilog: escape names that match SystemVerilog keywords.
whitequark
2019-01-27
1
-0
/
+27
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/
*
Add "write_edif -gndvccy"
Clifford Wolf
2019-01-17
1
-5
/
+13
*
Fix handling of $shiftx in Verilog back-end
Clifford Wolf
2019-01-15
1
-3
/
+6
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
4
-7
/
+7
*
Squelch a little more trailing whitespace
Larry Doolittle
2018-12-29
1
-3
/
+3
*
Minor style fixes
Clifford Wolf
2018-12-18
2
-1
/
+1
*
Add btor ops for $mul, $div, $mod and $concat
makaimann
2018-12-17
2
-2
/
+38
*
write_verilog: handle the $shift cell.
whitequark
2018-12-16
1
-0
/
+29
*
Merge pull request #736 from whitequark/select_assert_list
Clifford Wolf
2018-12-16
1
-1
/
+1
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write_verilog: add a missing newline.
whitequark
2018-12-16
1
-1
/
+1
*
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Merge pull request #729 from whitequark/write_verilog_initial
Clifford Wolf
2018-12-16
1
-0
/
+2
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*
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write_verilog: correctly map RTLIL `sync init`.
whitequark
2018-12-07
1
-0
/
+2
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/
*
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Add yosys-smtbmc support for btor witness
Clifford Wolf
2018-12-10
1
-15
/
+100
*
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Add "yosys-smtbmc --btorwit" skeleton
Clifford Wolf
2018-12-08
1
-1
/
+19
*
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Fix btor init value handling
Clifford Wolf
2018-12-08
1
-9
/
+13
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/
*
Add "write_aiger -I -O -B"
Clifford Wolf
2018-11-12
1
-2
/
+36
*
Merge pull request #693 from YosysHQ/rlimit
Clifford Wolf
2018-11-07
1
-8
/
+11
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*
Limit stack size to 16 MB on Darwin
Clifford Wolf
2018-11-07
1
-1
/
+4
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*
Fix for improved smtio.py rlimit code
Clifford Wolf
2018-11-06
1
-1
/
+1
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*
Improve stack rlimit code in smtio.py
Clifford Wolf
2018-11-06
1
-8
/
+8
*
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Run solver in non-incremental mode whem smtio.py is configured for non-increm...
Clifford Wolf
2018-11-06
1
-3
/
+12
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/
*
Use conservative stack size for SMT2 on MacOS
Arjen Roodselaar
2018-11-04
1
-1
/
+6
*
Add proper error message for when smtbmc "append" fails
Clifford Wolf
2018-11-04
1
-2
/
+10
*
Add support for signed $shift/$shiftx in smt2 back-end
Clifford Wolf
2018-11-01
1
-1
/
+3
*
adding offset info to memories
rafaeltp
2018-10-18
1
-1
/
+1
*
adding offset info to memories
rafaeltp
2018-10-18
1
-2
/
+3
*
Merge pull request #663 from aman-goel/master
Clifford Wolf
2018-10-17
1
-32
/
+51
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*
Minor update
Aman Goel
2018-10-15
1
-1
/
+1
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*
Update to .smv backend
Aman Goel
2018-10-01
1
-33
/
+52
*
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Add "write_edif -attrprop"
Clifford Wolf
2018-10-05
1
-11
/
+28
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/
*
added prefix to FDirection constants, fixing windows build
Miodrag Milanovic
2018-09-21
1
-11
/
+11
*
Fixed typo in "verilog_write" help message
acw1251
2018-09-18
1
-3
/
+3
*
Add $lut support to Verilog back-end
Clifford Wolf
2018-09-06
1
-0
/
+13
*
Remove unused functions.
Jim Lawson
2018-08-27
1
-10
/
+0
*
Add support for module instances.
Jim Lawson
2018-08-23
1
-17
/
+122
*
Merge pull request #591 from hzeller/virtual-override
Clifford Wolf
2018-08-15
15
-36
/
+36
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*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
15
-36
/
+36
*
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Merge pull request #576 from cr1901/no-resource
Clifford Wolf
2018-08-15
1
-9
/
+12
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*
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Gate POSIX-only signals and resource module to only run on POSIX Python imple...
William D. Jones
2018-07-06
1
-9
/
+12
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*
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Fix use of signed integers in JSON back-end
Clifford Wolf
2018-08-14
1
-1
/
+3
*
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Use `realpath`
jpathy
2018-08-06
1
-1
/
+1
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/
*
Fix protobuf build
Sergiusz Bazanski
2018-06-20
1
-1
/
+1
*
Add Protobuf backend
Serge Bazanski
2018-06-19
3
-0
/
+380
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