| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC. | whitequark | 2020-04-21 | 1 | -23/+23 |
| * | cxxrtl: use one delta cycle for immediately converging netlists. | whitequark | 2020-04-21 | 2 | -11/+21 |
| * | cxxrtl: add -O6, a shortcut for running `proc; flatten`. | whitequark | 2020-04-21 | 1 | -4/+14 |
| * | cxxrtl: unbuffer module input wires. | whitequark | 2020-04-21 | 1 | -31/+61 |
| * | cxxrtl: simplify generated edge detection logic. | whitequark | 2020-04-21 | 1 | -56/+29 |
| * | cxxrtl: localize wires with multiple comb drivers, too. | whitequark | 2020-04-21 | 1 | -32/+31 |
| * | cxxrtl: detect buffered comb wires, not just feedback wires. | whitequark | 2020-04-21 | 1 | -5/+40 |
| * | Merge pull request #1961 from whitequark/paramod-original-name | whitequark | 2020-04-21 | 1 | -11/+2 |
| |\ |
|
| | * | ast, rpc: record original name of $paramod\* as \hdlname attribute. | whitequark | 2020-04-18 | 1 | -11/+2 |
| * | | cxxrtl: provide attributes to black box factories, too. | whitequark | 2020-04-19 | 2 | -49/+57 |
| * | | cxxrtl: add templated black box support. | whitequark | 2020-04-18 | 1 | -16/+193 |
| * | | cxxrtl: make eval() and commit() inline in blackboxes. | whitequark | 2020-04-18 | 1 | -82/+103 |
| * | | cxxrtl: add simple black box support. | whitequark | 2020-04-18 | 2 | -70/+311 |
| * | | cxxrtl: use ID::X instead of ID(X). NFC. | whitequark | 2020-04-18 | 1 | -107/+107 |
| * | | cxxrtl: correctly handle `sync always` rules. | whitequark | 2020-04-17 | 1 | -3/+13 |
| |/ |
|
| * | Merge pull request #1947 from whitequark/cxxrtl-usability | whitequark | 2020-04-16 | 2 | -10/+19 |
| |\ |
|
| | * | cxxrtl: make ROMs writable, document memory::operator[]. | whitequark | 2020-04-16 | 2 | -4/+6 |
| | * | cxxrtl: fix misleading example, caution about race conditions. | whitequark | 2020-04-16 | 1 | -4/+13 |
| | * | cxxrtl: remove inaccurate comment. NFC. | whitequark | 2020-04-16 | 1 | -2/+0 |
| * | | Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfo | Claire Wolf | 2020-04-16 | 1 | -29/+51 |
| |\ \
| |/
|/| |
|
| | * | Fix indentation | Sahand Kashani | 2020-04-09 | 1 | -3/+3 |
| | * | Remove dependency on ilang backend since we no longer use it | Sahand Kashani | 2020-04-08 | 1 | -1/+0 |
| | * | Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo | Sahand Kashani | 2020-04-08 | 14 | -1131/+1243 |
| | |\ |
|
| | * | | Remove unnecessary pruning of double-quoting | Sahand Kashani | 2020-04-08 | 1 | -5/+0 |
| | * | | Remove use of auto for simple types + simplify src attribute computation | Sahand Kashani | 2020-03-24 | 1 | -10/+5 |
| | * | | Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src a... | Sahand Kashani | 2020-03-24 | 1 | -68/+15 |
| | * | | Indentation conventions | Sahand Kashani | 2020-03-23 | 1 | -5/+6 |
| | * | | Const parameter in function (backends/firrtl/firrtl.cc) | Sahand Kashani-Akhavan | 2020-03-23 | 1 | -1/+1 |
| | * | | Strip quotes around fileinfo strings | Sahand Kashani | 2020-03-21 | 1 | -1/+5 |
| | * | | Add fileinfo to firrtl backend for assignments and non-instance cells | Sahand Kashani | 2020-03-21 | 1 | -21/+30 |
| | * | | Refactor fileinfo emission characters to single location | Sahand Kashani | 2020-03-20 | 1 | -6/+8 |
| | * | | Add fileinfo to firrtl backend for instances | Sahand Kashani | 2020-03-19 | 1 | -2/+3 |
| | * | | Add fileinfo to firrtl backend for modules and wires | Sahand Kashani | 2020-03-19 | 1 | -12/+20 |
| | * | | Add fileinfo to firrtl backend for top-level circuit | Sahand Kashani | 2020-03-19 | 1 | -1/+62 |
| * | | | Merge pull request #1830 from boqwxp/qbfsat | N. Engelhardt | 2020-04-15 | 1 | -3/+15 |
| |\ \ \ |
|
| | * | | | Updated `yosys-smtbmc` to optionally dump raw bit strings, and fixed hole val... | Alberto Gonzalez | 2020-04-04 | 1 | -3/+15 |
| * | | | | json: Update format documentation. | Marcelina Kościelnicka | 2020-04-15 | 1 | -12/+32 |
| * | | | | cxxrtl: Fix handling of unclocked memory read ports | David Shah | 2020-04-14 | 1 | -2/+3 |
| * | | | | Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputs | whitequark | 2020-04-14 | 1 | -0/+2 |
| |\ \ \ \ |
|
| | * | | | | write_cxxrtl: ignore disconnected module ports. | whitequark | 2020-04-14 | 1 | -0/+2 |
| * | | | | | Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilation | whitequark | 2020-04-14 | 2 | -10/+82 |
| |\ \ \ \ \ |
|
| | * | | | | | write_verilog: fix precondition check. | whitequark | 2020-04-14 | 1 | -1/+1 |
| | * | | | | | write_cxxrtl: enable separate compilation. | whitequark | 2020-04-14 | 1 | -9/+81 |
| | |/ / / / |
|
| * / / / / | xaiger: add check for $__ABC9_DELAY model | Eddie Hung | 2020-04-13 | 1 | -0/+4 |
| |/ / / / |
|
| * | | | | Support custom PROGRAM_PREFIX | Miodrag Milanovic | 2020-04-10 | 2 | -9/+8 |
| * | | | | write_cxxrtl: add basic documentation. | whitequark | 2020-04-09 | 1 | -1/+16 |
| * | | | | write_cxxrtl: add support for $dlatch and $dlatchsr cells. | whitequark | 2020-04-09 | 1 | -3/+16 |
| * | | | | write_cxxrtl: add support for $sr cell. | whitequark | 2020-04-09 | 1 | -27/+35 |
| * | | | | write_cxxrtl: add support for $slice and $concat cells. | whitequark | 2020-04-09 | 1 | -1/+16 |
| * | | | | write_cxxrtl: improve writable memory handling. | whitequark | 2020-04-09 | 2 | -65/+87 |
