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| author | whitequark <whitequark@whitequark.org> | 2020-04-15 19:01:17 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-16 16:45:54 +0000 |
| commit | 58e89cd36879eb93f36a99ab2ee80cca101d0ec8 (patch) | |
| tree | 42e79fe034a348a2320cffe8291b15a78ad289e7 /backends | |
| parent | 3c4758c60e33386e19049d81fd6f72c8e7f316e0 (diff) | |
| download | yosys-58e89cd36879eb93f36a99ab2ee80cca101d0ec8.tar.gz yosys-58e89cd36879eb93f36a99ab2ee80cca101d0ec8.tar.bz2 yosys-58e89cd36879eb93f36a99ab2ee80cca101d0ec8.zip | |
cxxrtl: remove inaccurate comment. NFC.
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/cxxrtl/cxxrtl.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc index d1a855bf0..d6b901aa0 100644 --- a/backends/cxxrtl/cxxrtl.cc +++ b/backends/cxxrtl/cxxrtl.cc @@ -1425,8 +1425,6 @@ struct CxxrtlWorker { if (cell->getPort(ID(CLK)).is_wire()) register_edge_signal(sigmap, cell->getPort(ID(CLK)), cell->parameters[ID(CLK_POLARITY)].as_bool() ? RTLIL::STp : RTLIL::STn); - // The $adff and $dffsr cells are level-sensitive, not edge-sensitive (in spite of the fact that they - // are inferred from an edge-sensitive Verilog process) and do not correspond to an edge-type sync rule. } // Similar for memory port cells. if (cell->type.in(ID($memrd), ID($memwr))) { |