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* Add "write_aiger -L"Clifford Wolf2019-09-181-5/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix stupid bug in btor back-endClifford Wolf2019-09-181-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* backends: smt2: use $(CXX) variable for compilerSean Cross2019-09-081-1/+1
| | | | | | | | | | | The Makefile assumes the compiler is called `gcc`, which isn't always true. In fact, if we're building on msys2 or msys2-64, the compiler is called `i686-w64-mingw32-g++` or `x86_64-w64-mingw32-g++`. Use the variable instead of hardcoding the name, to fix building on these systems. Signed-off-by: Sean Cross <sean@xobs.io>
* Recognise built-in types (e.g. $_DFF_*)Eddie Hung2019-08-301-3/+3
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* Revert "Revert "Fix omode which inserts an output if none exists (otherwise ↵Eddie Hung2019-08-281-7/+8
| | | | | | abc9 breaks)"" This reverts commit 8f0c1232d7c511a6473f4581e4c27a90088cedb7.
* Revert "Output "h" extension only if boxes"Eddie Hung2019-08-281-32/+28
| | | | This reverts commit 399ac760ff2bf4a7d438ed388820e7bfb511de6b.
* Output "h" extension only if boxesEddie Hung2019-08-211-28/+32
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* Revert "Fix omode which inserts an output if none exists (otherwise abc9 ↵Eddie Hung2019-08-211-8/+7
| | | | | | breaks)" This reverts commit 8182cb9d91555d5be52abbfeeb5d22af05342d8a.
* Fix omode which inserts an output if none exists (otherwise abc9 breaks)Eddie Hung2019-08-201-7/+8
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* Revert "Only xaig if GetSize(output_bits) > 0"Eddie Hung2019-08-201-149/+147
| | | | This reverts commit 7b646101e936cacd20938c20ddfbaa63ee268fb2.
* Only xaig if GetSize(output_bits) > 0Eddie Hung2019-08-201-147/+149
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* Remove sequential extensionEddie Hung2019-08-201-270/+29
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* Do not sigmap!Eddie Hung2019-08-201-2/+2
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* Minor refactorEddie Hung2019-08-201-7/+6
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* Output i/o/h extensions even if no boxes or flopsEddie Hung2019-08-191-65/+66
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* Add (* abc_arrival *) attributeEddie Hung2019-08-191-9/+66
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-191-1/+1
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| * Fix various NDEBUG compiler warnings, closes #1255Clifford Wolf2019-08-131-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Use %dEddie Hung2019-08-191-1/+1
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* | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1612-209/+353
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| * | Compute abc_scc_break and move CI/CO outside of each abc9Eddie Hung2019-08-161-42/+0
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| * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-109-33/+33
| |\ | | | | | | Cleanup a few barnacles across codebase
| | * substr() -> compare()Eddie Hung2019-08-075-6/+6
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| | * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-074-12/+12
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| | * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-106/+240
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| | * | Use IdString::begins_with()Eddie Hung2019-08-061-2/+2
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| | * | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-061-5/+5
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| | * | Use State::S{0,1}Eddie Hung2019-08-063-6/+6
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| | * | Make liberal use of IdString.in()Eddie Hung2019-08-062-2/+2
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| * | | Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cellClifford Wolf2019-08-101-1/+1
| |\ \ \ | | | | | | | | | | FIRRTL error on unsupported cell
| | * \ \ Merge branch 'master' into firrtl_err_on_unsupported_cellJim Lawson2019-08-079-116/+287
| | |\ \ \ | | | | |/ | | | |/| | | | | | | | | | | # Conflicts: # backends/firrtl/firrtl.cc
| | * | | Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ↵Jim Lawson2019-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | backend.
| * | | | Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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| * | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-071-93/+203
| |\ \ \ | | | | | | | | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
| | * | | Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-311-93/+203
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
| * | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-071-13/+37
| |\ \ \ | | |_|/ | |/| | Improved JSON attr/param encoding
| | * | Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-066-3/+40
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-1/+1
| |\ \ | | | | | | | | Visual Studio build fix
| | * | Visual Studio build fixMiodrag Milanovic2019-07-311-1/+1
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| * / Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-6/+6
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| * Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
| |\ | | | | | | write_verilog: dump zero width constants correctly
| | * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again).
| * | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * smt: handle failure of setrlimit syscallN. Engelhardt2019-07-151-1/+5
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| * Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
| |\ | | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| | * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
* | | abc_flop to also get topologically sortedEddie Hung2019-07-101-11/+10
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* | | Fix clk_pol for FD*_1Eddie Hung2019-07-101-1/+0
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* | | Fix spacingEddie Hung2019-07-101-1/+1
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