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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-066-3/+40
* Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-1/+1
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| * Visual Studio build fixMiodrag Milanovic2019-07-311-1/+1
* | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-6/+6
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* Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
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| * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
* | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
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* smt: handle failure of setrlimit syscallN. Engelhardt2019-07-151-1/+5
* Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
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| * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
* | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-positionClifford Wolf2019-07-091-3/+2
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| * | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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* | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscoreEddie Hung2019-07-091-4/+6
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| * Rename __builtin_bswap32 -> bswap32Eddie Hung2019-07-091-4/+6
* | verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
* | verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
* | Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-0/+5
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* write_xaiger to treat unknown cell connections as keep-sEddie Hung2019-07-021-6/+14
* Add generic __builtin_bswap32 functionEddie Hung2019-06-281-0/+15
* Also fix write_aiger for UBEddie Hung2019-06-281-26/+26
* Fix more potential for undefined behaviour due to container invalidationEddie Hung2019-06-281-6/+10
* Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-42/+40
* Merge origin/masterEddie Hung2019-06-272-4/+31
* Improve debugging message for comb loopsEddie Hung2019-06-261-4/+6
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-241-0/+4
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| * Fix json formattingMiodrag Milanovic2019-06-211-1/+1
| * Add upto and offset to JSON portsMiodrag Milanovic2019-06-211-0/+4
* | Carry in/out box ordering now move to end, not swap with endEddie Hung2019-06-221-26/+34
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-0/+4
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| * Added JSON upto and offsetClifford Wolf2019-06-211-0/+4
| * Fix gcc invalidation behaviour for write_aigerEddie Hung2019-06-201-1/+2
* | Replace assert with error messageEddie Hung2019-06-211-1/+2
* | Add log_push()/log_pop() inside write_xaigerEddie Hung2019-06-211-0/+4
* | One more workaround for gcc-4.8Eddie Hung2019-06-211-3/+4
* | No point logging constant bitEddie Hung2019-06-211-1/+1
* | Move commentEddie Hung2019-06-211-2/+3
* | Fix spacingEddie Hung2019-06-201-1/+1
* | Refactor bit2aig for less lookupsEddie Hung2019-06-201-24/+27
* | Fix gcc invalidation behaviour for write_aigerEddie Hung2019-06-201-1/+2
* | Fix gcc error, due to dict invalidation during recursionEddie Hung2019-06-201-2/+3
* | write_xaiger to flatten 1'bx/1'bz to 1'b0 againEddie Hung2019-06-201-2/+4
* | Fix different abc9 testEddie Hung2019-06-201-2/+3
* | Fix broken abc9.v test due to inout being 1'bxEddie Hung2019-06-201-2/+11
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-205-0/+6
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| * Support filename rewrite in backendsBen Widawsky2019-06-184-0/+4
| * Add timescale and generated-by header to yosys-smtbmc MkVcdClifford Wolf2019-06-161-0/+2
* | Handle COs driven by 1'bxEddie Hung2019-06-201-3/+9
* | write_xaiger to skip POs driven by 1'bxEddie Hung2019-06-201-3/+7
* | CleanupEddie Hung2019-06-161-228/+25
* | Leave breadcrumb behindEddie Hung2019-06-141-0/+2