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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:21:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:37:54 -0700 |
| commit | f2d541962e92fedce0fbb34d4cf5c1985c7cda40 (patch) | |
| tree | 2d594ad525f41f30d8084970570d9bc1241a6b78 /backends | |
| parent | 8e0a47fb920af1126adb67f884b5ce1443a9b4a9 (diff) | |
| download | yosys-f2d541962e92fedce0fbb34d4cf5c1985c7cda40.tar.gz yosys-f2d541962e92fedce0fbb34d4cf5c1985c7cda40.tar.bz2 yosys-f2d541962e92fedce0fbb34d4cf5c1985c7cda40.zip | |
write_xaiger to skip POs driven by 1'bx
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 1485e2b0c..12b23cfe9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -152,9 +152,13 @@ struct XAigerWriter } if (wire->port_output || keep) { - if (bit != wirebit) - alias_map[wirebit] = bit; - output_bits.insert(wirebit); + if (bit != RTLIL::Sx) { + if (bit != wirebit) + alias_map[wirebit] = bit; + output_bits.insert(wirebit); + } + else + log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); } } } |