iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
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*	Adde "write_verilog -renameprefix -v"	Clifford Wolf	2016-11-01	1	-5/+23
*	Bugfix in partial mem write handling in verilog back-end	Clifford Wolf	2016-08-20	1	-42/+26
*	Added missing support for mem read enable ports to verilog back-end	Clifford Wolf	2016-08-18	1	-6/+14
*	Fixed upto handling in verilog back-end	Clifford Wolf	2016-08-15	1	-0/+3
*	Added "write_verilog -defparam"	Clifford Wolf	2016-07-30	1	-2/+21
*	Added "write_verilog -nodec -nostr"	Clifford Wolf	2016-07-30	1	-4/+27
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Bugfix in write_verilog for RTLIL processes	Clifford Wolf	2016-03-14	1	-9/+20
*	Bugfixes in writing of memories as Verilog	Clifford Wolf	2015-09-25	1	-7/+8
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-2/+2
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-3/+3
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-4/+4
*	$mem cell in verilog backend : grouped writes by clock	luke whittlesey	2015-06-08	1	-54/+108
*	Bug fix in $mem verilog backend + changed tests/bram flow of make test.	luke whittlesey	2015-06-04	1	-14/+16
*	Some fixes for $mem in verilog back-end	Clifford Wolf	2015-05-20	1	-19/+23
*	Merge pull request #63 from wluker/verilog-backend-mem	Clifford Wolf	2015-05-11	1	-1/+2
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\| *	Fixed bug in $mem cell verilog code generation.	luke whittlesey	2015-05-11	1	-11/+12
* \|	Disabled broken $mem support in verilog backend	Clifford Wolf	2015-05-10	1	-11/+11
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*	Made changes recommended by Clifford Wolf ...	luke whittlesey	2015-05-10	1	-22/+11
*	Verilog backend for $mem cells should now be able to handle different	luke whittlesey	2015-05-08	1	-50/+105
*	Added support for $mem cells in the verilog backend.	luke whittlesey	2015-05-07	1	-1/+120
*	Minor fixes in handling of "init" attribute	Clifford Wolf	2015-04-09	1	-7/+7
*	Added "init" attribute support to verilog backend	Clifford Wolf	2015-04-04	1	-0/+5
*	Added Verilog backend $dffsr support	Clifford Wolf	2015-03-18	1	-1/+51
*	Fixed "write_verilog -attr2comment" handling of "*/" in strings	Clifford Wolf	2015-02-13	1	-2/+4
*	Added dict/pool.sort()	Clifford Wolf	2015-01-24	1	-0/+2
*	Cosmetic changes in verilog output format	Clifford Wolf