iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added Verilog backend $dffsr support	Clifford Wolf	2015-03-18	1	-1/+51
*	Fixed "write_verilog -attr2comment" handling of "*/" in strings	Clifford Wolf	2015-02-13	1	-2/+4
*	Added dict/pool.sort()	Clifford Wolf	2015-01-24	1	-0/+2
*	Cosmetic changes in verilog output format	Clifford Wolf	2015-01-02	1	-5/+10
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26	1	-25/+25
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-1/+1
*	Added $dffe support to write_verilog	Clifford Wolf	2014-12-20	1	-3/+14
*	Fixed generation of temp names in verilog backend	Clifford Wolf	2014-11-07	1	-4/+5
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	2	-42/+3
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	1	-1/+2
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-1/+0
*	Using $pos models for $bu0	Clifford Wolf	2014-09-03	1	-16/+1
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	2	-233/+232
*	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16	1	-4/+4
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-4/+40
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-1/+1
*	Refactoring of CellType class	Clifford Wolf	2014-08-14	1	-10/+28
*	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02	1	-2/+3
*	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02	1	-3/+19
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-6/+6
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-40/+40
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	1	-9/+22
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-3/+2
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-4/+4
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-2/+2
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-4/+4
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-43/+43
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-43/+43
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-21/+29
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-3/+0
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-29/+29
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-29/+29
*	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...	Clifford Wolf	2014-07-20	1	-17/+21
*	Added support for $bu0 to verilog backend	Clifford Wolf	2014-07-20	1	-0/+16
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+22
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-6/+8
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-8/+11
*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24	1	-4/+6
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-7/+7
*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21	1	-1/+44
*	Write yosys version to output files	Clifford Wolf	2013-11-03	1	-2/+2
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-1/+1
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	1	-4/+4
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	1	-0/+1
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-28/+1