iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	1	-1/+1
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
\| \| \| \| \| \| \| \| \|	o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -- c++ -- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
*	Also escape "=" in spice output	Clifford Wolf	2016-05-20	1	-1/+1
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
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*	Fixed some typos	Clifford Wolf	2016-04-05	1	-1/+1
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*	Be more conservative with net names in spice output	Clifford Wolf	2016-03-02	1	-18/+47
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
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*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-1/+1
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
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*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-26/+26
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-2/+2
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-4/+4
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-1/+1
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-4/+4
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-4/+4
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-9/+7
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-11/+11
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-11/+11
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	1	-0/+5
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-2/+2
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*	Silenced a gcc warning in spice backend	Clifford Wolf	2013-11-09	1	-1/+1
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*	Write yosys version to output files	Clifford Wolf	2013-11-03	1	-4/+1
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*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-1/+1
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*	A couple of small fixes in SPICE backend	Clifford Wolf	2013-09-15	1	-6/+18
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*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14	1	-3/+0
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*	Added spice backend	Clifford Wolf	2013-09-14	2	-0/+228