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Author
Age
Files
Lines
*
namespace Yosys
Clifford Wolf
2014-09-27
1
-0
/
+4
*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
1
-26
/
+26
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
1
-1
/
+1
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-2
/
+2
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-1
/
+0
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-4
/
+4
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-2
/
+2
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-4
/
+4
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-4
/
+4
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
1
-9
/
+7
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-11
/
+11
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-11
/
+11
*
Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
1
-0
/
+5
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
1
-2
/
+2
*
Silenced a gcc warning in spice backend
Clifford Wolf
2013-11-09
1
-1
/
+1
*
Write yosys version to output files
Clifford Wolf
2013-11-03
1
-4
/
+1
*
Fixed handling of boolean attributes (backends)
Clifford Wolf
2013-10-24
1
-1
/
+1
*
A couple of small fixes in SPICE backend
Clifford Wolf
2013-09-15
1
-6
/
+18
*
Added spice testbench to techlibs/cmos
Clifford Wolf
2013-09-14
1
-3
/
+0
*
Added spice backend
Clifford Wolf
2013-09-14
2
-0
/
+228