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* Use (and ignore) the expression provided to log_assert in NDEBUG builds.whitequark2020-06-191-2/+0
* Use C++11 final/override keywords.whitequark2020-06-181-4/+4
* Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+2
* ilang, ast: Store parameter order and default value information.Marcelina Koƛcielnicka2020-04-211-2/+10
* Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`.Alberto Gonzalez2020-04-011-6/+6
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-4/+4
* Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-0/+5
* Support filename rewrite in backendsBen Widawsky2019-06-181-0/+1
* Add "real" keyword to ilang formatClifford Wolf2019-05-061-1/+4
* Fix a syntax bug in ilang backend related to process case statementsClifford Wolf2019-03-141-1/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
* Fixed gcc 7.2 "statement will never be executed" warningClifford Wolf2018-02-031-1/+1
* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-0/+7
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-0/+1
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-022-5/+5
* Shorter "dump" optionsClifford Wolf2015-01-311-4/+4
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-0/+2
* Added dict/pool.sort()Clifford Wolf2015-01-241-50/+24
* Fixed memory->start_offset handlingClifford Wolf2015-01-011-0/+2
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-17/+17
* namespace YosysClifford Wolf2014-09-271-0/+6
* Sorting of object names in ilang backendClifford Wolf2014-09-192-21/+49
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-232-134/+132
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-312-4/+8
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-281-0/+2
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-3/+2
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-2/+2
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-251-2/+2
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-4/+4
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-4/+4
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-211-1/+14
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-131-0/+1
* Added support for dump -appendClifford Wolf2014-02-041-3/+12
* Updated manual/command-reference-manual.texClifford Wolf2013-12-281-1/+1
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-041-1/+1
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-8/+11
* Added dump -m and -n optionsClifford Wolf2013-11-292-54/+89
* Added support for signed parameters in ilangClifford Wolf2013-11-241-1/+1
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-241-2/+0
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-211-0/+1
* Write yosys version to output filesClifford Wolf2013-11-031-0/+1
* Added -selected option to various backendsClifford Wolf2013-09-031-3/+20
* Fixed generation of newlines in "dump" outputClifford Wolf2013-06-101-3/+4
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-022-13/+103