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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
| commit | f9946232adf887e5aa4a48c64f88eaa17e424009 (patch) | |
| tree | 39594b3287c3369752668456c4a6b1735fb66e77 /backends/ilang | |
| parent | d7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff) | |
| download | yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.gz yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.bz2 yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.zip | |
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'backends/ilang')
| -rw-r--r-- | backends/ilang/ilang_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 6678f19d2..c0b7dab9a 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -280,7 +280,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module if (print_body) { - for (auto it = module->wires.begin(); it != module->wires.end(); it++) + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) if (!only_selected || design->selected(module, it->second)) { if (only_selected) fprintf(f, "\n"); |