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Author
Age
Files
Lines
*
Fix btor init value handling
Clifford Wolf
2018-12-08
1
-9
/
+13
*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-2
/
+2
*
Add "no driver for signal bit" error msg to btor back-end
Clifford Wolf
2017-12-24
1
-0
/
+2
*
Simple fix BTOR memory encoding
Clifford Wolf
2017-12-17
1
-2
/
+2
*
Improve BTOR memory encoding
Clifford Wolf
2017-12-17
1
-2
/
+16
*
Add array support to btor back-end
Clifford Wolf
2017-12-15
1
-6
/
+169
*
Add $anyconst/$anyseq support to btor back-end
Clifford Wolf
2017-12-15
1
-13
/
+51
*
Add "write_btor -s" mode
Clifford Wolf
2017-12-13
1
-6
/
+50
*
Add state initval handling to btor back-end
Clifford Wolf
2017-12-12
1
-0
/
+25
*
Add btor back-end support for 'x' constants
Clifford Wolf
2017-12-12
1
-1
/
+54
*
Add btor $shift/$shiftx support
Clifford Wolf
2017-12-11
2
-7
/
+37
*
Fix btor back-end shift handling
Clifford Wolf
2017-12-10
2
-5
/
+7
*
Add support for $pmux in btor back-end
Clifford Wolf
2017-12-10
1
-0
/
+23
*
Add support for more cell types to btor back-end
Clifford Wolf
2017-12-10
2
-6
/
+245
*
Fix btor concat
Clifford Wolf
2017-12-09
1
-1
/
+1
*
Bugfixes in new BTOR back-end
Clifford Wolf
2017-11-24
1
-2
/
+3
*
Progress in new BTOR back-end
Clifford Wolf
2017-11-23
1
-36
/
+97
*
Progress in new BTOR back-end
Clifford Wolf
2017-11-23
1
-3
/
+95
*
Progress in new BTOR back-end
Clifford Wolf
2017-11-23
1
-14
/
+72
*
Progress with new BTOR backend
Clifford Wolf
2017-11-23
1
-8
/
+109
*
Add skeleton for new BTOR back-end
Clifford Wolf
2017-11-23
2
-0
/
+216
*
Remove old BTOR back-end
Clifford Wolf
2017-11-23
4
-1174
/
+0
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
1
-1
/
+1
*
Renamed opt_const to opt_expr
Clifford Wolf
2016-03-31
1
-1
/
+1
*
Added "int ceil_log2(int)" function
Clifford Wolf
2016-02-13
1
-8
/
+8
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
1
-1
/
+1
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
1
-2
/
+2
*
Remove some very strange whitespace in btor.cc (by Larry Doolittle)
Clifford Wolf
2015-08-05
1
-7
/
+7
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
3
-89
/
+89
*
Fixed cstr_buf for std::string with small string optimization
Clifford Wolf
2015-06-11
1
-1
/
+1
*
Removed "techmap -share_map" (use "-map +/filename" instead)
Clifford Wolf
2015-04-08
1
-1
/
+1
*
Update README
Ahmed Irfan
2015-04-03
1
-1
/
+1
*
Delete btor.ys
Ahmed Irfan
2015-04-03
1
-18
/
+0
*
Update README
Ahmed Irfan
2015-04-03
1
-1
/
+1
*
separated memory next from write cell
Ahmed Irfan
2015-04-03
1
-7
/
+55
*
Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
1
-2
/
+2
*
namespace Yosys
Clifford Wolf
2014-09-27
1
-0
/
+4
*
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Ahmed Irfan
2014-09-22
2
-199
/
+199
|
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*
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...
Clifford Wolf
2014-09-01
1
-1
/
+2
|
*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
1
-65
/
+65
|
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
1
-1
/
+1
|
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
1
-11
/
+11
|
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-34
/
+34
|
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
1
-1
/
+3
|
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-1
/
+1
|
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-2
/
+2
|
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-3
/
+3
|
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-2
/
+2
|
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
1
-34
/
+34
|
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-4
/
+4
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