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author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:08:55 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:27:48 +0200 |
commit | 7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch) | |
tree | 563de1df5e323d0f217a51e29acb56c9e9f1327d /backends/btor | |
parent | d86a25f145012ccb6b2048af3aae22f13b97b505 (diff) | |
download | yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.gz yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.bz2 yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.zip |
Using log_assert() instead of assert()
Diffstat (limited to 'backends/btor')
-rw-r--r-- | backends/btor/btor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 4af121005..f721fdc99 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -549,7 +549,7 @@ struct BtorDumper int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); l1_width = pow(2, ceil(log(l1_width)/log(2))); int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int(); - //assert(l2_width <= ceil(log(l1_width)/log(2)) ); + //log_assert(l2_width <= ceil(log(l1_width)/log(2)) ); int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width); int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2))); int cell_output = ++line_num; |