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author | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
commit | 84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch) | |
tree | c19a405bc106c2472f1aaa46c36b189db3e5223f /backends/btor | |
parent | 80910d13a610886f4430fbd991ada78b2e586ada (diff) | |
download | yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.gz yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.bz2 yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.zip |
Spell check (by Larry Doolittle)
Diffstat (limited to 'backends/btor')
-rw-r--r-- | backends/btor/btor.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 6f02d3078..26585f43b 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -70,7 +70,7 @@ struct BtorDumper CellTypes ct; SigMap sigmap; - std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for maping the intermediate wires that are output of some cell + std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for mapping the intermediate wires that are output of some cell std::map<RTLIL::IdString, int> line_ref;//mapping of ids to line_num of the btor file std::map<RTLIL::SigSpec, int> sig_ref;//mapping of sigspec to the line_num of the btor file int line_num;//last line number of btor file @@ -722,7 +722,7 @@ struct BtorDumper //registers else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr") { - //TODO: remodelling fo adff cells + //TODO: remodelling of adff cells log("writing cell - %s\n", cstr(cell->type)); int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int(); log(" - width is %d\n", output_width); |