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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Renamed opt_const to opt_exprClifford Wolf2016-03-311-1/+1
* Added "int ceil_log2(int)" functionClifford Wolf2016-02-131-8/+8
* Another block of spelling fixesLarry Doolittle2015-08-141-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-2/+2
* Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-051-7/+7
* Fixed trailing whitespacesClifford Wolf2015-07-023-89/+89
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-111-1/+1
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-081-1/+1
* Update READMEAhmed Irfan2015-04-031-1/+1
* Delete btor.ysAhmed Irfan2015-04-031-18/+0
* Update READMEAhmed Irfan2015-04-031-1/+1
* separated memory next from write cellAhmed Irfan2015-04-031-7/+55
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-2/+2
* namespace YosysClifford Wolf2014-09-271-0/+4
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-222-199/+199
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| * Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+2
| * Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-65/+65
| * No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
| * More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-11/+11
| * Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-34/+34
| * Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-1/+3
| * Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
| * Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-2/+2
| * Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
| * Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-2/+2
| * More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-34/+34
| * Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-34/+34
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-34/+34
| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-251-21/+21
| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-2/+2
| * SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-40/+40
| * SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-40/+40
| * Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-071-18/+17
* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-181-8/+27
* | added $pmux cell translationAhmed Irfan2014-09-021-2/+38
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* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-122-6/+6
* disabling splice command in the scriptAhmed Irfan2014-02-112-2/+6
* register output correctedAhmed Irfan2014-02-111-1/+1
* added concat and slice cell translationAhmed Irfan2014-02-113-36/+59
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-061-1/+1
* Added BTOR backend README fileClifford Wolf2014-02-052-1/+24
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-032-1/+6
* root bug correctedAhmed Irfan2014-01-251-1/+5
* removed regex includeAhmed Irfan2014-01-241-1/+0
* merged clifford changes + removed regexAhmed Irfan2014-01-241-26/+52
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-242-2/+2
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-242-0/+50
* slice bug correctedAhmed Irfan2014-01-201-1/+1
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