| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -1/+1 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -2/+2 |
| * | Remove some very strange whitespace in btor.cc (by Larry Doolittle) | Clifford Wolf | 2015-08-05 | 1 | -7/+7 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 3 | -89/+89 |
| * | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 | 1 | -1/+1 |
| * | Removed "techmap -share_map" (use "-map +/filename" instead) | Clifford Wolf | 2015-04-08 | 1 | -1/+1 |
| * | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 |
| * | Delete btor.ys | Ahmed Irfan | 2015-04-03 | 1 | -18/+0 |
| * | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 |
| * | separated memory next from write cell | Ahmed Irfan | 2015-04-03 | 1 | -7/+55 |
| * | Added ENABLE_NDEBUG makefile options | Clifford Wolf | 2015-01-24 | 1 | -2/+2 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor | Ahmed Irfan | 2014-09-22 | 2 | -199/+199 |
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| | * | Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::... | Clifford Wolf | 2014-09-01 | 1 | -1/+2 |
| | * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 1 | -65/+65 |
| | * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| | * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -11/+11 |
| | * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -34/+34 |
| | * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -1/+3 |
| | * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+1 |
| | * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| | * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| | * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| | * | More RTLIL::Cell API usage cleanups | Clifford Wolf | 2014-07-26 | 1 | -34/+34 |
| | * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| | * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -34/+34 |
| | * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -34/+34 |
| | * | Various RTLIL::SigSpec related code cleanups | Clifford Wolf | 2014-07-25 | 1 | -21/+21 |
| | * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| | * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -40/+40 |
| | * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -40/+40 |
| | * | Use log_abort() and log_assert() in BTOR backend | Clifford Wolf | 2014-03-07 | 1 | -18/+17 |
| * | | fixed memory next issue, when same memory is written in different case statement | ahmedirfan1983 | 2014-09-18 | 1 | -8/+27 |
| * | | added $pmux cell translation | Ahmed Irfan | 2014-09-02 | 1 | -2/+38 |
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| * | modified btor synthesis script for correct use of splice command. | Ahmed Irfan | 2014-02-12 | 2 | -6/+6 |
| * | disabling splice command in the script | Ahmed Irfan | 2014-02-11 | 2 | -2/+6 |
| * | register output corrected | Ahmed Irfan | 2014-02-11 | 1 | -1/+1 |
| * | added concat and slice cell translation | Ahmed Irfan | 2014-02-11 | 3 | -36/+59 |
| * | Fixed gcc compiler warnings with release build | Clifford Wolf | 2014-02-06 | 1 | -1/+1 |
| * | Added BTOR backend README file | Clifford Wolf | 2014-02-05 | 2 | -1/+24 |
| * | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) | Clifford Wolf | 2014-02-03 | 2 | -1/+6 |
| * | root bug corrected | Ahmed Irfan | 2014-01-25 | 1 | -1/+5 |
| * | removed regex include | Ahmed Irfan | 2014-01-24 | 1 | -1/+0 |
| * | merged clifford changes + removed regex | Ahmed Irfan | 2014-01-24 | 1 | -26/+52 |
| * | Use techmap -share_map in btor scripts | Clifford Wolf | 2014-01-24 | 2 | -2/+2 |
| * | Moved btor scripts to backends/btor/ | Clifford Wolf | 2014-01-24 | 2 | -0/+50 |
| * | slice bug corrected | Ahmed Irfan | 2014-01-20 | 1 | -1/+1 |
| * | assert feature | Ahmed Irfan | 2014-01-20 | 1 | -9/+40 |
| * | verilog default options pull | Ahmed Irfan | 2014-01-17 | 1 | -28/+97 |
| * | slice error corrected | Ahmed Irfan | 2014-01-16 | 1 | -5/+5 |
