Commit message (Expand) | Author | Age | Files | Lines | |
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* | Bump version | Yosys Bot | 2020-09-24 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-22 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-19 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-18 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-11 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-04 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-03 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-02 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-09-01 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-30 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-29 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-28 | 1 | -1/+1 |
* | Merge pull request #2357 from whitequark/cxxflags-MP | whitequark | 2020-08-27 | 1 | -1/+1 |
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| * | Add -MP to CXXFLAGS. | whitequark | 2020-08-26 | 1 | -1/+1 |
* | | Merge pull request #2358 from whitequark/rename-ilang-to-rtlil | whitequark | 2020-08-27 | 1 | -3/+3 |
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| * | | Replace "ILANG" with "RTLIL" everywhere. | whitequark | 2020-08-26 | 1 | -3/+3 |
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* / | Bump version | Yosys Bot | 2020-08-27 | 1 | -1/+1 |
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* | Bump version | Yosys Bot | 2020-08-23 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-21 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-20 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-19 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-14 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-13 | 1 | -1/+1 |
* | Bump version | Yosys Bot | 2020-08-10 | 1 | -1/+1 |
* | Bump YOSYS_VER | Claire Wolf | 2020-07-31 | 1 | -1/+1 |
* | Add utility module for representing flip-flops. | Marcelina Kościelnicka | 2020-07-23 | 1 | -0/+1 |
* | Add utility module for dealing with init attributes. | Marcelina Kościelnicka | 2020-07-23 | 1 | -0/+1 |
* | satgen: Move importCell out of the header. | Marcelina Kościelnicka | 2020-07-19 | 1 | -1/+1 |
* | Fix issue #2251 (#2252) | Lucas Castro | 2020-07-09 | 1 | -1/+1 |
* | Add option to use ccache when building | Dan Ravensloft | 2020-07-04 | 1 | -0/+5 |
* | Update ABC. | whitequark | 2020-06-22 | 1 | -1/+1 |
* | cxxrtl: add missing installs of include files. | whitequark | 2020-06-08 | 1 | -0/+5 |
* | Merge pull request #2051 from Xiretza/makefile-cd-warning | whitequark | 2020-05-28 | 1 | -1/+1 |
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| * | Suppress warning during initial clone of ABC repo | Xiretza | 2020-05-14 | 1 | -1/+1 |
* | | Setup tests/verilog properly | Eddie Hung | 2020-05-11 | 1 | -0/+1 |
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* | Remove yosys libdir from LDFLAGS (and fix a typo) | N. Engelhardt | 2020-05-07 | 1 | -2/+1 |
* | Makefile: git fetch all commits from $(ABCURL) repo | Eddie Hung | 2020-05-06 | 1 | -1/+1 |
* | Update ABC to include WASI support fixes. | whitequark | 2020-05-02 | 1 | -1/+1 |
* | Fix WASI builds with abc enabled. | whitequark | 2020-05-01 | 1 | -2/+2 |
* | Merge pull request #2001 from whitequark/wasi | whitequark | 2020-05-01 | 1 | -1/+47 |
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| * | Add WASI platform support. | whitequark | 2020-04-30 | 1 | -2/+48 |
* | | Merge pull request #1997 from whitequark/document-ootb | Claire Wolf | 2020-05-01 | 1 | -11/+11 |
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| * | Fix out-of-tree builds configured as `SMALL := 1`. | whitequark | 2020-04-24 | 1 | -11/+11 |
* | | abc: use YosysHQ/abc instead of upstream berkeley-abc/abc | Eddie Hung | 2020-04-27 | 1 | -2/+2 |
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* | Merge pull request #1900 from Xiretza/suppress-makefile-echo | whitequark | 2020-04-16 | 1 | -0/+3 |
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| * | Suppress output of Makefile.conf when printing source versions | Xiretza | 2020-04-11 | 1 | -0/+3 |
* | | synth_intel_alm: alternative synthesis for Intel FPGAs | Dan Ravensloft | 2020-04-15 | 1 | -0/+1 |
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* | Keep libyosys name same as befire, but put it in directory | Miodrag Milanovic | 2020-04-10 | 1 | -11/+11 |
* | Support custom PROGRAM_PREFIX | Miodrag Milanovic | 2020-04-10 | 1 | -43/+44 |
* | write_cxxrtl: new backend. | whitequark | 2020-04-09 | 1 | -0/+1 |