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| author | whitequark <whitequark@whitequark.org> | 2020-08-27 11:24:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-27 11:24:06 +0000 |
| commit | 702f7c0253dcf9410050586a5e56da044e3277a3 (patch) | |
| tree | ab94c9121ceb78152a538843e82f69228e938dde /Makefile | |
| parent | 880df4c89763464b471b1e2044f3f296bb3332b4 (diff) | |
| parent | 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e (diff) | |
| download | yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.gz yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.bz2 yosys-702f7c0253dcf9410050586a5e56da044e3277a3.zip | |
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
Replace "ILANG" with "RTLIL" everywhere
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -593,7 +593,7 @@ $(eval $(call add_include_file,libs/sha1/sha1.h)) $(eval $(call add_include_file,libs/json11/json11.hpp)) $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,frontends/ast/ast.h)) -$(eval $(call add_include_file,backends/ilang/ilang_backend.h)) +$(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.cc)) @@ -634,7 +634,7 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc else include $(YOSYS_SRC)/frontends/verilog/Makefile.inc -include $(YOSYS_SRC)/frontends/ilang/Makefile.inc +include $(YOSYS_SRC)/frontends/rtlil/Makefile.inc include $(YOSYS_SRC)/frontends/ast/Makefile.inc include $(YOSYS_SRC)/frontends/blif/Makefile.inc @@ -651,7 +651,7 @@ include $(YOSYS_SRC)/passes/opt/Makefile.inc include $(YOSYS_SRC)/passes/techmap/Makefile.inc include $(YOSYS_SRC)/backends/verilog/Makefile.inc -include $(YOSYS_SRC)/backends/ilang/Makefile.inc +include $(YOSYS_SRC)/backends/rtlil/Makefile.inc include $(YOSYS_SRC)/techlibs/common/Makefile.inc |