| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx | Eddie Hung | 2019-08-22 | 2 | -4/+96 | |
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| | * | | | | Copy-paste typo | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
| | * | | | | Respect opt_expr -keepdc as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -1/+15 | |
| | * | | | | Handle $shift and Y_WIDTH > 1 as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -5/+51 | |
| | * | | | | Add cover() | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
| | * | | | | Canonical form | Eddie Hung | 2019-08-22 | 1 | -5/+5 | |
| | * | | | | Add test | Eddie Hung | 2019-08-21 | 1 | -0/+14 | |
| | * | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 | |
| * | | | | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 | |
| * | | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| * | | | | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 109 | -3621/+4745 | |
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| | * | | | | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 | |
| * | | | | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| * | | | | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 | |
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| | * | | | | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
| | * | | | | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 | |
| | * | | | | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 | |
| | * | | | | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 | |
| | * | | | | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
| | * | | | | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 | |
| | * | | | | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 | |
| | * | | | | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
| | * | | | | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 58 | -598/+1321 | |
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| | * | | | | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
| | * | | | | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
| | * | | | | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
| | * | | | | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
| * | | | | | | | | Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg | Clifford Wolf | 2019-08-22 | 2 | -0/+17 | |
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| | * | | | | | | | | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| * | | | | | | | | Merge pull request #1315 from mmicko/fix_dependencies | whitequark | 2019-08-21 | 1 | -1/+1 | |
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| | * | | | | | | | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 4 | -4/+21 | |
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| | * | | | | | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| | * | | | | | | | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 | |
| | * | | | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
| * | | | | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| * | | | | | | | | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 5 | -16/+23 | |
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| | * \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 191 | -4502/+7003 | |
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| | * | | | | | | | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 | |
| | * | | | | | | | | Update changelog | Eddie Hung | 2019-07-22 | 1 | -3/+4 | |
| | * | | | | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| | * | | | | | | | | Add CHANGELOG entry | Eddie Hung | 2019-07-18 | 1 | -0/+3 | |
| | * | | | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 | |
| * | | | | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 6 | -104/+138 | |
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| | * | | | | | | | | | Clarify with 'only' | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
| | * | | | | | | | | | Update doc | Eddie Hung | 2019-08-19 | 1 | -3/+4 | |
| | * | | | | | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 4 | -12/+12 | |
| | * | | | | | | | | | Use ID() | Eddie Hung | 2019-08-16 | 1 | -3/+3 | |
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index : iCE40/yosys | |
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