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Author
Age
Files
Lines
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Do not swap if equals
Eddie Hung
2019-07-15
1
-1
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+1
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SigSpec::extend_u0() to return *this
Eddie Hung
2019-07-15
2
-2
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+3
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Oops forgot these files
Eddie Hung
2019-07-15
3
-2
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+12
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Add xilinx_dsp for register packing
Eddie Hung
2019-07-15
3
-2
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+192
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OUT port to Y in generic DSP
Eddie Hung
2019-07-15
2
-3
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+3
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Move DSP mapping back out to dsp_map.v
Eddie Hung
2019-07-15
2
-41
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+40
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Only swap if B_WIDTH > A_WIDTH
Eddie Hung
2019-07-15
1
-1
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+1
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Tidy up
Eddie Hung
2019-07-15
1
-39
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+26
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Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim
Eddie Hung
2019-07-15
2
-82
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+131
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-07-15
16
-30
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+639
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Merge pull request #1194 from cr1901/miss-semi
Eddie Hung
2019-07-14
1
-2
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+2
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Fix missing semicolon in Windows-specific code in aigerparse.cc.
William D. Jones
2019-07-14
1
-2
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+2
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Merge pull request #1183 from whitequark/ice40-always-relut
Clifford Wolf
2019-07-12
1
-11
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+5
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synth_ice40: switch -relut to be always on.
whitequark
2019-07-11
1
-10
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+4
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synth_ice40: fix help text typo. NFC.
whitequark
2019-07-11
1
-1
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+1
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Merge pull request #1182 from koriakin/xc6s-bram
Eddie Hung
2019-07-11
9
-8
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+598
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synth_xilinx: Initial Spartan 6 block RAM inference support.
Marcin Kościelnicki
2019-07-11
9
-8
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+598
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Merge pull request #1185 from koriakin/xc-ff-init-vals
Eddie Hung
2019-07-11
2
-6
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+6
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xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...
Marcin Kościelnicki
2019-07-11
2
-6
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+6
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Enable &mfs for abc9, even if it only currently works for ice40
Eddie Hung
2019-07-11
1
-1
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+1
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Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
Clifford Wolf
2019-07-11
1
-2
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+8
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write_verilog: write RTLIL::Sa aka - as Verilog ?.
whitequark
2019-07-09
1
-2
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+8
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Merge pull request #1179 from whitequark/attrmap-proc
Clifford Wolf
2019-07-11
1
-0
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+19
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attrmap: also consider process, switch and case attributes.
whitequark
2019-07-10
1
-0
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+19
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Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little
Eddie Hung
2019-07-10
4
-45
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+42
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-07-10
34
-271
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+734
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Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Eddie Hung
2019-07-10
3
-6
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+15
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Error out if -abc9 and -retime specified
Eddie Hung
2019-07-10
3
-6
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+15
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Merge pull request #1148 from YosysHQ/xc7mux
Eddie Hung
2019-07-10
7
-49
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+415
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Add some spacing
Eddie Hung
2019-07-10
1
-9
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+9
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Add some ASCII art explaining mux decomposition
Eddie Hung
2019-07-10
1
-0
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+21
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Call muxpack and pmux2shiftx before cmp2lut
Eddie Hung
2019-07-09
1
-9
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+12
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Restore opt_clean back to original place
Eddie Hung
2019-07-09
1
-2
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+1
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Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
Eddie Hung
2019-07-09
1
-0
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+2
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Extend using A[1] to preserve don't care
Eddie Hung
2019-07-09
1
-1
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+9
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Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux
Eddie Hung
2019-07-09
2
-4
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+9
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Extend during mux decomposition with 1'bx
Eddie Hung
2019-07-09
1
-24
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+3
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Fix typo and comments
Eddie Hung
2019-07-09
1
-4
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+4
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-07-09
16
-79
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+348
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synth_xilinx to call commands of synth -coarse directly
Eddie Hung
2019-07-09
1
-3
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+20
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Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
Eddie Hung
2019-07-09
1
-2
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+2
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Fix spacing
Eddie Hung
2019-07-09
1
-1
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+1
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Fix spacing
Eddie Hung
2019-07-09
1
-1
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+1
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Decompose mux inputs in delay-orientated (rather than area) fashion
Eddie Hung
2019-07-08
1
-18
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+30
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Do not call opt -mux_undef (part of -full) before muxcover
Eddie Hung
2019-07-08
1
-1
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+5
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Add one more comment
Eddie Hung
2019-07-08
1
-0
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+3
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Less thinking
Eddie Hung
2019-07-08
1
-3
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+3
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Reword
Eddie Hung
2019-07-08
1
-2
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+2
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synth_xilinx to call "synth -run coarse" with "-keepdc"
Eddie Hung
2019-07-08
1
-2
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+2
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Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux
Eddie Hung
2019-07-08
4
-8
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+25
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