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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 12:20:04 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 12:20:04 -0700 |
commit | 521971e32ef54fa64474a8ed1c2748572901aaf5 (patch) | |
tree | b7da5a872cb317cb841ea1e01998291590f73c91 | |
parent | e573d024a257a6cf8925784f6f22d192a1f24693 (diff) | |
download | yosys-521971e32ef54fa64474a8ed1c2748572901aaf5.tar.gz yosys-521971e32ef54fa64474a8ed1c2748572901aaf5.tar.bz2 yosys-521971e32ef54fa64474a8ed1c2748572901aaf5.zip |
Add some ASCII art explaining mux decomposition
-rw-r--r-- | techlibs/xilinx/cells_map.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index f20fe253e..82399be08 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -214,6 +214,27 @@ module \$__XILINX_SHIFTX (A, B, Y); assign Ax = {A[1], A}; \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y)); end + // Note that the following decompositions are 'backwards' in that + // the LSBs are placed on the hard resources, and the soft resources + // are used for MSBs. + // This has the effect of more effectively utilising the hard mux; + // take for example a 5:1 multiplexer, currently this would map as: + // + // A[0] \___ __ A[0] \__ __ + // A[4] / \| \ whereas the more A[1] / \| \ + // A[1] _____| | obvious mapping A[2] \___| | + // A[2] _____| |-- of MSBs to hard A[3] / | |__ + // A[3]______| | resources would A[4] ____| | + // |__/ lead to: 1'bx ____| | + // || |__/ + // || || + // B[1:0] B[1:2] + // + // Expectation would be that the 'forward' mapping (right) is more + // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers + // on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs) + // but that the 'backwards' mapping (left) is more delay efficient + // since smaller LUTs are faster than wider ones. else if (A_WIDTH <= 8) begin wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A}; wire T0 = B[2] ? Ax[4] : Ax[0]; |