aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorwhitequark <whitequark@whitequark.org>2019-07-10 12:28:32 +0000
committerwhitequark <whitequark@whitequark.org>2019-07-10 12:30:53 +0000
commitea447220dab2a5a66adb3a78ca2789068f046f3a (patch)
tree887de36fd38da74486efef3a09e214c140326410
parent27b27b8781ab8d57aa85a432aba7e914570feffb (diff)
downloadyosys-ea447220dab2a5a66adb3a78ca2789068f046f3a.tar.gz
yosys-ea447220dab2a5a66adb3a78ca2789068f046f3a.tar.bz2
yosys-ea447220dab2a5a66adb3a78ca2789068f046f3a.zip
attrmap: also consider process, switch and case attributes.
-rw-r--r--passes/techmap/attrmap.cc19
1 files changed, 19 insertions, 0 deletions
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index aa48e1125..a38638e0b 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -263,6 +263,25 @@ struct AttrmapPass : public Pass {
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes);
+
+ for (auto proc : module->processes)
+ {
+ if (!design->selected(module, proc.second))
+ continue;
+ attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes);
+
+ std::vector<RTLIL::CaseRule*> all_cases = {&proc.second->root_case};
+ while (!all_cases.empty()) {
+ RTLIL::CaseRule *cs = all_cases.back();
+ all_cases.pop_back();
+ attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes);
+
+ for (auto &sw : cs->switches) {
+ attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes);
+ all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end());
+ }
+ }
+ }
}
}
}