iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	recover_reduce_core: Initial commit	Robert Ou	2017-08-27	2	-0/+110
\| \| \| \| \|	Conflicts: passes/techmap/Makefile.inc
*	Don't track , ... contradictions through x/z-bits	Clifford Wolf	2017-08-25	1	-1/+4
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*	Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr	Clifford Wolf	2017-08-25	1	-0/+72
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*	Merge branch 'extract_fa'	Clifford Wolf	2017-08-25	2	-0/+502
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\| *	Further improve extract_fa (seems to be fully functional now)	Clifford Wolf	2017-08-25	1	-10/+226
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\| *	Rename "adders" to "extract_fa"	Clifford Wolf	2017-08-25	2	-28/+16
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\| *	Towards more generic "adder" function extractor	Clifford Wolf	2017-08-23	1	-202/+53
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\| *	Add experimental adders pass	Clifford Wolf	2017-08-22	2	-0/+447
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* \|	Fix bug in write_smt2 (export logic driving hierarchical cells before ↵	Clifford Wolf	2017-08-25	1	-34/+34
\|/ \| \| \|	exporting regs)
*	Add hashlib support for hashing of pools	Clifford Wolf	2017-08-22	1	-0/+7
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*	Add consteval support for $_ANDNOT_ and $_ORNOT_	Clifford Wolf	2017-08-22	1	-0/+4
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*	Remove some dead code from fsm_map	Clifford Wolf	2017-08-21	1	-3/+0
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*	Rename "singleton" pass to "uniquify"	Clifford Wolf	2017-08-20	3	-21/+22
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*	More intuitive handling of "cd .." for singleton modules	Clifford Wolf	2017-08-19	1	-2/+38
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*	Add "sim -zinit -rstlen"	Clifford Wolf	2017-08-18	1	-1/+53
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*	Merge branch 'sim'	Clifford Wolf	2017-08-18	4	-0/+848
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\| *	Add "sim" support for memories	Clifford Wolf	2017-08-18	1	-2/+136
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\| *	Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()	Clifford Wolf	2017-08-18	2	-0/+37
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\| *	Add support for assert/assume/cover to "sim" command	Clifford Wolf	2017-08-18	1	-4/+47
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\| *	Add writeback mode to "sim" command	Clifford Wolf	2017-08-17	1	-0/+44
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\| *	Improve "sim" command	Clifford Wolf	2017-08-17	1	-54/+272
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\| *	Add "sim" command skeleton	Clifford Wolf	2017-08-16	2	-0/+372
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* \|	Merge pull request #386 from azonenberg/gpak-counters	Clifford Wolf	2017-08-16	1	-73/+82
\|\ \ \| \|/ \|/\|	Bug fixes to GP_COUNTx and GP_PGEN cells in GreenPAK technology library
\| *	Fixed more issues with GreenPAK counter sim models	Andrew Zonenberg	2017-08-15	1	-19/+23
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\| *	Updated PGEN model to have level triggered reset (matches actual hardware ↵	Andrew Zonenberg	2017-08-15	1	-4/+4
\| \| \| \| \| \| \| \|	behavior
\| *	Fixed bug in GP_COUNTx model	Andrew Zonenberg	2017-08-15	1	-7/+12
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\| *	Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high	Andrew Zonenberg	2017-08-15	1	-47/+47
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*	Merge branch 'azonenberg-rmports'	Clifford Wolf	2017-08-15	2	-0/+188
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\| *	Mostly coding style related fixes in rmports pass	Clifford Wolf	2017-08-15	1	-30/+33
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\| *	Merge branch 'rmports' of https://github.com/azonenberg/yosys into ↵	Clifford Wolf	2017-08-15	2	-0/+185
\|/\| \| \| \| \| \| \|	azonenberg-rmports
\| *	rmports: Now remove ports from cell instances if we optimized them out of ↵	Andrew Zonenberg	2017-08-14	1	-2/+35
\| \| \| \| \| \| \| \|	that cell
\| *	ProcessModule is no longer virtual (why was it in the first place?)	Andrew Zonenberg	2017-08-14	1	-1/+1
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\| *	rmports now works on all modules in the design, not just the top.	Andrew Zonenberg	2017-08-14	1	-4/+7
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\| *	Updated Makefile to reflect opt_rmports being renamed to rmports	Andrew Zonenberg	2017-08-14	1	-1/+1
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\| *	Renamed opt_rmports pass to rmports	Andrew Zonenberg	2017-08-14	1	-5/+5
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\| *	Improved handling of constant connections in opt_rmports	Andrew Zonenberg	2017-08-14	1	-0/+2
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\| *	Fixed handling of cell ports that aren't wires	Andrew Zonenberg	2017-08-14	1	-0/+3
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\| *	opt_rmports: Fixed incorrect handling of multi-bit nets	Andrew Zonenberg	2017-08-14	1	-12/+27
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\| *	Removed commented out debug code	Andrew Zonenberg	2017-08-14	1	-4/+0
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\| *	Added opt_rmports pass (remove unconnected ports from top-level modules)	Andrew Zonenberg	2017-08-14	2	-0/+133
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* \|	Merge pull request #381 from azonenberg/countfix	Clifford Wolf	2017-08-14	4	-504/+900
\|\ \ \| \| \| \| \| \|	Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
\| * \|	Fixed typo in GP_COUNT8 sim model	Andrew Zonenberg	2017-08-14	1	-1/+1
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\| * \|	Fixed typo in error message	Andrew Zonenberg	2017-08-14	1	-1/+1
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\| * \|	Changed LEVEL resets for GP_COUNTx to be properly synthesizeable	Andrew Zonenberg	2017-08-14	1	-48/+60
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\| * \|	Changed LEVEL resets to be edge triggered anyway	Andrew Zonenberg	2017-08-14	1	-4/+4
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\| * \|	Added level-triggered reset support to GP_COUNTx simulation models	Andrew Zonenberg	2017-08-14	1	-2/+68
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\| * \|	Fixed undeclared "count" in GP_COUNT8_ADV	Andrew Zonenberg	2017-08-14	1	-0/+2
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\| * \|	Fixed undeclared "count" in GP_COUNT14_ADV	Andrew Zonenberg	2017-08-14	1	-0/+2
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\| * \|	Fixed typo in last commit	Andrew Zonenberg	2017-08-14	1	-3/+3
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\| * \|	Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock ↵	Andrew Zonenberg	2017-08-14	2	-37/+293
\| \| \| \| \| \| \| \| \| \| \| \|	divide, but do everything else.