aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLarry Doolittle <ldoolitt@recycle.lbl.gov>2018-12-28 08:24:31 -0800
committerClifford Wolf <clifford@clifford.at>2018-12-29 12:46:54 +0100
commit99706b3bf48de121e58b76d4341d601f0bcc26cd (patch)
tree80aa3f8cbc000adc228a7a0ca3bbd70225f2f19a
parent245724a504528156485bbb32710b5e5444899ce1 (diff)
downloadyosys-99706b3bf48de121e58b76d4341d601f0bcc26cd.tar.gz
yosys-99706b3bf48de121e58b76d4341d601f0bcc26cd.tar.bz2
yosys-99706b3bf48de121e58b76d4341d601f0bcc26cd.zip
Squelch a little more trailing whitespace
-rw-r--r--backends/simplec/test00_uut.v6
-rw-r--r--tests/sva/basic01.sv2
2 files changed, 4 insertions, 4 deletions
diff --git a/backends/simplec/test00_uut.v b/backends/simplec/test00_uut.v
index 744dbe9e3..92329a6f9 100644
--- a/backends/simplec/test00_uut.v
+++ b/backends/simplec/test00_uut.v
@@ -3,12 +3,12 @@ module test(input [31:0] a, b, c, output [31:0] x, y, z, w);
unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
assign z = a ^ b ^ c, w = z;
endmodule
-
+
module unit_x(input [31:0] a, b, c, output [31:0] x);
assign x = (a & b) | c;
endmodule
-
+
module unit_y(input [31:0] a, b, c, output [31:0] y);
assign y = a & (b | c);
endmodule
-
+
diff --git a/tests/sva/basic01.sv b/tests/sva/basic01.sv
index 74ab93430..d5ad497dd 100644
--- a/tests/sva/basic01.sv
+++ b/tests/sva/basic01.sv
@@ -6,7 +6,7 @@ module top (input logic clock, ctrl);
write <= ctrl;
ready <= write;
end
-
+
a_rw: assert property ( @(posedge clock) !(read && write) );
`ifdef FAIL
a_wr: assert property ( @(posedge clock) write |-> ready );