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author | Clifford Wolf <clifford@clifford.at> | 2018-12-31 15:52:01 +0100 |
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committer | GitHub <noreply@github.com> | 2018-12-31 15:52:01 +0100 |
commit | e09e49ca5415d721b395fa5de4124cca50a6908b (patch) | |
tree | 31c72860993327e71fc7c59458d3b5e54b2c6560 | |
parent | ebe9351f82279f83ef16a24faac9853d40b3ece1 (diff) | |
parent | 1b369442995ea3f83d0d0445bb34c8f8115c10a3 (diff) | |
download | yosys-e09e49ca5415d721b395fa5de4124cca50a6908b.tar.gz yosys-e09e49ca5415d721b395fa5de4124cca50a6908b.tar.bz2 yosys-e09e49ca5415d721b395fa5de4124cca50a6908b.zip |
Merge pull request #766 from Icenowy/anlogic-latches
anlogic: add latch cells
-rw-r--r-- | techlibs/anlogic/cells_map.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v index 36b920ef0..f54a81dcc 100644 --- a/techlibs/anlogic/cells_map.v +++ b/techlibs/anlogic/cells_map.v @@ -15,6 +15,18 @@ module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REG module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule + `ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; |