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* tests/xilinx: fix flaky mux testMarcin Kościelnicki2019-12-181-2/+4
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* xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-1811-27/+638
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* xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-188-49/+242
| | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
* Send people to symbioticeda.com instead of verific.comClifford Wolf2019-12-182-5/+26
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-1613-65/+529
|\ | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| * Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵Eddie Hung2019-12-161-2/+8
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| | * Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
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| * | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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| * Disable RAM16X1D testEddie Hung2019-12-131-17/+17
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| * Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
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| * RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
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| * Remove extraneous synth_xilinx callEddie Hung2019-12-121-2/+0
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| * Add tests for these new modelsEddie Hung2019-12-121-0/+40
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| * Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
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| * Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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| * Add #1460 testcaseEddie Hung2019-12-121-0/+34
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| * Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
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| * Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-129-53/+156
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* | Merge pull request #1521 from dh73/diego/memattrEddie Hung2019-12-167-48/+374
|\ \ | | | | | | Adding support for Xilinx memory attribute 'block' in single port mode.
| * | Enforce non-existenceEddie Hung2019-12-161-0/+4
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| * | Update docEddie Hung2019-12-161-4/+6
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| * | Add another testEddie Hung2019-12-161-1/+8
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| * | More sloppiness, thanks @dh73 for spottingEddie Hung2019-12-161-4/+4
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| * | Accidentally commented out testsEddie Hung2019-12-161-47/+47
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| * | Add unconditional match blocks for force RAMEddie Hung2019-12-162-4/+45
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| * | OopsEddie Hung2019-12-161-4/+1
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| * | Merge blockram testsEddie Hung2019-12-163-47/+81
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| * | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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| * | Implement 'attributes' grammarEddie Hung2019-12-161-80/+88
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| * | Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattrEddie Hung2019-12-164-1/+238
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| * | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-162-14/+14
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| * | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-152-3242/+4
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| * | Merging attribute rules into a single match block; Adding testsDiego H2019-12-155-86/+3465
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| * | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-132-0/+96
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* | | Merge pull request #1575 from rodrigomelo9/masterEddie Hung2019-12-153-4/+4
|\ \ \ | | | | | | | | Fixed some missing "verilog_" in documentation
| * | | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-133-4/+4
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* | | Merge pull request #1577 from gromero/for-yosysEddie Hung2019-12-151-1/+1
|\ \ \ | | | | | | | | manual: Fix text in Abstract section
| * | | manual: Fix text in Abstract sectionGustavo Romero2019-12-111-1/+1
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* | | | Merge pull request #1578 from noopwafel/eqneq-debugEddie Hung2019-12-151-1/+1
|\ \ \ \ | |_|_|/ |/| | | Fix opt_expr.eqneq.cmpzero debug print
| * | | Fix opt_expr.eqneq.cmpzero debug printAlyssa Milburn2019-12-151-1/+1
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* | | Merge pull request #1533 from dh73/bram_xilinxEddie Hung2019-12-133-6/+101
|\ \ \ | |_|/ |/| | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
| * | Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-132-6/+6
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| * | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-122-7/+7
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| * | Adding a note (TODO) in the memory_params.ys check fileDiego H2019-12-121-0/+2
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| * | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-123-2/+92
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| * | Merge https://github.com/YosysHQ/yosys into bram_xilinxDiego H2019-12-1243-1053/+2108
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| * | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
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* | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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* | | Update README.md :: abc_ -> abc9_Eddie Hung2019-12-111-3/+3
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* | | Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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