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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:31:15 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:31:15 -0800 |
| commit | 5a00d5578cea91ce84f3d95e6138c85d1a949b89 (patch) | |
| tree | 6734b8efe4366ebccc958c302984aa2be9d5601a | |
| parent | 6b384861e4b1e02b24bf11d266cf11f461115cd8 (diff) | |
| download | yosys-5a00d5578cea91ce84f3d95e6138c85d1a949b89.tar.gz yosys-5a00d5578cea91ce84f3d95e6138c85d1a949b89.tar.bz2 yosys-5a00d5578cea91ce84f3d95e6138c85d1a949b89.zip | |
Add unconditional match blocks for force RAM
| -rw-r--r-- | techlibs/xilinx/xc7_xcu_brams.txt | 40 | ||||
| -rw-r--r-- | tests/arch/xilinx/blockram.ys | 9 |
2 files changed, 45 insertions, 4 deletions
diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 60425fed9..c63218ae1 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,7 +77,7 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -86,8 +86,16 @@ match $__XILINX_RAMB36_SDP or_next_if_better endmatch +match $__XILINX_RAMB36_SDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB18_SDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -96,8 +104,16 @@ match $__XILINX_RAMB18_SDP or_next_if_better endmatch +match $__XILINX_RAMB18_SDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB36_TDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -106,12 +122,28 @@ match $__XILINX_RAMB36_TDP or_next_if_better endmatch +match $__XILINX_RAMB36_TDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB18_TDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp endmatch diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 362d33229..b6e105854 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 |