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* Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmapEddie Hung2019-08-2716-223/+1075
|\ | | | | Add clock buffer insertion pass, improve iopadmap.
| * improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-272-6/+45
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| * Improve tests to check that clkbuf is connected to expectedEddie Hung2019-08-261-6/+21
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| * Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-268-60/+405
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| * \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| * \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-233-18/+36
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| * | | | Check clkbuf_inhibit=1 is ignored for custom selectionEddie Hung2019-08-231-0/+1
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| * | | | clkbufmap to only check clkbuf_inhibit if no selection givenEddie Hung2019-08-231-5/+18
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| * | | | Add simple clkbufmap testsEddie Hung2019-08-231-0/+52
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| * | | | tests/techmap/run-test.sh to cope with *.ysEddie Hung2019-08-232-7/+18
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| * | | | Mention clkbuf_inhibit can be overriddenEddie Hung2019-08-231-7/+8
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| * | | | Review comment from @cliffordwolfEddie Hung2019-08-231-1/+2
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| * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-23146-1486/+4373
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1657-3403/+3432
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| * | | | | | README updatesMarcin Kościelnicki2019-08-131-0/+14
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| * | | | | | move attributes to wiresMarcin Kościelnicki2019-08-138-311/+546
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| * | | | | | minor review fixesMarcin Kościelnicki2019-08-132-3/+5
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| * | | | | | review fixesMarcin Kościelnicki2019-08-134-47/+34
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| * | | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-1310-93/+577
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | | | | | Add "make bumpversion"Clifford Wolf2019-08-272-0/+4
| |_|_|_|_|/ |/| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Remove dupe in CHANGELOG, missing end quoteEddie Hung2019-08-261-2/+1
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* | | | | | Merge tag 'yosys-0.9'Clifford Wolf2019-08-262-11/+107
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| * | | | | | Yosys 0.9Clifford Wolf2019-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Revert earliest to gcc-4.8, compile iverilog with default compilerEddie Hung2019-08-232-3/+3
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| * | | | | | Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"Eddie Hung2019-08-231-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d.
| * | | | | | Remove .0 from clang-8.0Eddie Hung2019-08-231-2/+2
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| * | | | | | Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!Eddie Hung2019-08-231-3/+5
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| * | | | | | bionic -> xenial as its on whitelistEddie Hung2019-08-231-1/+1
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| * | | | | | Bump gcc from 4.8 to 4.9 as undefined referenceEddie Hung2019-08-231-35/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to `__warn_memset_zero_len'. Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
| * | | | | | Make macOS depenency clearMiodrag Milanovic2019-08-231-2/+5
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| * | | | | | do not require boost if pyosys is not usedMiodrag Milanovic2019-08-221-0/+2
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| * | | | | | require tcl-tk in BrewfileChris Shucksmith2019-08-221-0/+1
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| * | | | | | Bump year in copyright noticeClifford Wolf2019-08-223-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Visual Studio build fixMiodrag Milanovic2019-08-021-0/+1
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| * | | | | | Fix linking issue for new mxe and pthreadMiodrag Milanovic2019-08-021-1/+2
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| * | | | | | Fix yosys linking for mxeMiodrag Milanovic2019-08-021-1/+1
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| * | | | | | New mxe hacks needed to support 2ca237eMiodrag Milanovic2019-08-021-0/+4
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| * | | | | | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-028-17/+20
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| * | | | | | Update CHANGELOGDavid Shah2019-07-261-10/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-positionClifford Wolf2019-07-091-3/+2
| | | | | | | | | | | | | | | | | | | | | write_verilog: fix placement of case attributes
| * | | | | | Update CHANGELOGDavid Shah2019-07-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | Merge pull request #1163 from whitequark/more-case-attrsClifford Wolf2019-07-093-16/+28
| | | | | | | | | | | | | | | | | | | | | More support for case rule attributes
| * | | | | | Merge pull request #1162 from whitequark/rtlil-case-attrsClifford Wolf2019-07-093-5/+15
| | | | | | | | | | | | | | | | | | | | | Allow attributes on individual switch cases in RTLIL
| * | | | | | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wireClifford Wolf2019-07-091-0/+3
| | | | | | | | | | | | | | | | | | | | | Throw runtime exception when trying to convert inexistend C++ object to Python
| * | | | | | Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-093-82/+26
| | | | | | | | | | | | | | | | | | | | | Improve specify dummy parser
| * | | | | | Merge pull request #1154 from whitequark/manual-sync-alwaysClifford Wolf2019-07-091-2/+3
| | | | | | | | | | | | | | | | | | | | | manual: explain the purpose of `sync always`
| * | | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_muxDavid Shah2019-07-093-3/+25
| | | | | | | | | | | | | | | | | | | | | memory_dff: Fix checking of feedback mux input when more than one mux
| * | | | | | Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-07-091-1/+1
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| * | | | | | Merge pull request #1146 from gsomlo/gls-test-abc-extClifford Wolf2019-07-094-8/+29
| | | | | | | | | | | | | | | | | | | | | tests: use optional ABCEXTERNAL when specified
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