| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'upstream/master' | Jim Lawson | 2019-07-30 | 21 | -32/+164 |
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| | * | Merge pull request #1228 from YosysHQ/dave/yy_buf_size | Eddie Hung | 2019-07-29 | 1 | -0/+3 |
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| | | * | verilog_lexer: Increase YY_BUF_SIZE to 65536 | David Shah | 2019-07-26 | 1 | -0/+3 |
| | * | | Merge pull request #1234 from mmicko/fix_gzip_no_exist | David Shah | 2019-07-29 | 1 | -19/+21 |
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| | | * | | Fix case when file does not exist | Miodrag Milanovic | 2019-07-29 | 1 | -19/+21 |
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| | * | | Merge pull request #1226 from YosysHQ/dave/gzip | David Shah | 2019-07-27 | 8 | -13/+70 |
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| | | * | Update CHANGELOG | David Shah | 2019-07-26 | 1 | -1/+1 |
| | | * | Fix frontend auto-detection for gzipped input | David Shah | 2019-07-26 | 1 | -9/+12 |
| | | * | Add support for reading gzip'd input files | David Shah | 2019-07-26 | 6 | -3/+57 |
| | * | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-07-25 | 17 | -29/+360 |
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| | | * \ | Merge branch 'ZirconiumX-synth_intel_m9k' | Clifford Wolf | 2019-07-25 | 4 | -5/+11 |
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| | | | * | | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 4 | -5/+12 |
| | | * | | | Merge pull request #1218 from ZirconiumX/synth_intel_iopads | Clifford Wolf | 2019-07-25 | 1 | -8/+8 |
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| | | | * | | | intel: Make -noiopads the default | Dan Ravensloft | 2019-07-24 | 1 | -8/+8 |
| | | * | | | | Merge pull request #1219 from jakobwenzel/objIterator | Clifford Wolf | 2019-07-25 | 2 | -3/+20 |
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| | | | * | | | | replaced std::iterator with using statements | Jakob Wenzel | 2019-07-25 | 1 | -6/+6 |
| | | | * | | | | made ObjectIterator extend std::iterator | Jakob Wenzel | 2019-07-24 | 2 | -2/+19 |
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| | | * | | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ff | Eddie Hung | 2019-07-25 | 1 | -2/+2 |
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| | | | * | | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 |
| | | * | | | | Merge pull request #1222 from koriakin/s6-example | Eddie Hung | 2019-07-24 | 5 | -0/+47 |
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| | | | * | | | Add a simple example for Spartan 6 | Marcin Kościelnicki | 2019-07-24 | 5 | -0/+47 |
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| | * | | | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 |
| * | | | | | Merge remote-tracking branch 'upstream/master' | Jim Lawson | 2019-07-24 | 199 | -1214/+9423 |
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| | * | | | | Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp | Eddie Hung | 2019-07-23 | 3 | -9/+241 |
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| | | * | | | | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 |
| | | * | | | | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 |
| | | * | | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 |
| | | * | | | | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 |
| | | * | | | | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
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| | * | | | | Merge pull request #1214 from jakobwenzel/astmod_clone | Eddie Hung | 2019-07-22 | 1 | -0/+2 |
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| | | * | | | initialize noblackbox and nowb in AstModule::clone | Jakob Wenzel | 2019-07-22 | 1 | -0/+2 |
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| | * / / | Add "stat -tech cmos" | Clifford Wolf | 2019-07-20 | 1 | -2/+29 |
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| | * | | Merge pull request #1208 from ZirconiumX/intel_cleanups | David Shah | 2019-07-18 | 1 | -29/+14 |
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| | | * | | synth_intel: Use stringf | Dan Ravensloft | 2019-07-18 | 1 | -7/+2 |
| | | * | | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 |
| | | * | | synth_intel: revert change to run_max10 | Dan Ravensloft | 2019-07-18 | 1 | -1/+1 |
| | | * | | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 |
| | | * | | intel_synth: Small code cleanup to remove if ladder | Ben Widawsky | 2019-07-18 | 2 | -29/+11 |
| | | * | | intel_synth: Make family explicit and match | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| | | * | | intel_synth: Minor code cleanups | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| | * | | | Merge pull request #1207 from ZirconiumX/intel_new_pass_names | David Shah | 2019-07-18 | 1 | -4/+4 |
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| | | * | | synth_intel: rename for consistency with #1184 | Dan Ravensloft | 2019-07-18 | 1 | -4/+4 |
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| | * | | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 5 | -17/+21 |
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| | | * | | synth_ecp5: rename dram to lutram everywhere. | whitequark | 2019-07-16 | 4 | -13/+13 |
| | | * | | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 2 | -5/+9 |
| | * | | | Merge pull request #1203 from whitequark/write_verilog-zero-width-values | Clifford Wolf | 2019-07-18 | 1 | -1/+2 |
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| | | * | | | write_verilog: dump zero width constants correctly. | whitequark | 2019-07-16 | 1 | -1/+2 |
| | * | | | | Remove old $pmux_safe code from write_verilog | Clifford Wolf | 2019-07-17 | 1 | -5/+4 |
| | * | | | | Merge pull request #1204 from smunaut/fix_1187 | David Shah | 2019-07-17 | 2 | -4/+4 |
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| | | * | | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 2 | -4/+4 |
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index : iCE40/yosys | |
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