diff options
author | Clifford Wolf <clifford@clifford.at> | 2019-07-25 17:23:48 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2019-07-25 17:23:48 +0200 |
commit | eb663c75794d1249247ba88bf0bee835c98a8a85 (patch) | |
tree | 8a3f1374d980bd05695e83a3f01a6d9a31f8fd48 | |
parent | 5c933e511046d1720b74e47a6919c3f88ca8d303 (diff) | |
parent | 67b4ce06e07fde80d5ac11cad4d673c501bdd421 (diff) | |
download | yosys-eb663c75794d1249247ba88bf0bee835c98a8a85.tar.gz yosys-eb663c75794d1249247ba88bf0bee835c98a8a85.tar.bz2 yosys-eb663c75794d1249247ba88bf0bee835c98a8a85.zip |
Merge branch 'ZirconiumX-synth_intel_m9k'
-rw-r--r-- | techlibs/intel/Makefile.inc | 4 | ||||
-rw-r--r-- | techlibs/intel/common/brams_m9k.txt (renamed from techlibs/intel/common/brams.txt) | 0 | ||||
-rw-r--r-- | techlibs/intel/common/brams_map_m9k.v (renamed from techlibs/intel/common/brams_map.v) | 0 | ||||
-rw-r--r-- | techlibs/intel/synth_intel.cc | 12 |
4 files changed, 11 insertions, 5 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index ec7cea379..7a3d2c71a 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -3,8 +3,8 @@ OBJS += techlibs/intel/synth_intel.o $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v)) diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams_m9k.txt index 3bf21afc9..3bf21afc9 100644 --- a/techlibs/intel/common/brams.txt +++ b/techlibs/intel/common/brams_m9k.txt diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map_m9k.v index d0f07c1de..d0f07c1de 100644 --- a/techlibs/intel/common/brams_map.v +++ b/techlibs/intel/common/brams_map_m9k.v diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 539ba379f..e5dc1adc7 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -187,8 +187,15 @@ struct SynthIntelPass : public ScriptPass { } if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/intel/common/brams.txt"); - run("techmap -map +/intel/common/brams_map.v"); + if (family_opt == "cycloneiv" || + family_opt == "cycloneive" || + family_opt == "max10" || + help_mode) { + run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)"); + run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)"); + } else { + log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str()); + } } if (check_label("map_ffram")) { @@ -218,7 +225,6 @@ struct SynthIntelPass : public ScriptPass { if (iopads || help_mode) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)"); run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); - run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); } |