iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| *	Refine memory support to deal with general Verilog memory definitions.	Jim Lawson	2019-04-01	1	-30/+173
* \|	Merge pull request #895 from YosysHQ/pmux2shiftx	Eddie Hung	2019-04-02	1	-0/+28
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\| *	Create one $shiftx per bit in width	Eddie Hung	2019-03-25	1	-10/+17
\| *	Add a pmux-to-shiftx optimisation to proc_mux	Eddie Hung	2019-03-23	1	-0/+21
* \|	Merge pull request #907 from YosysHQ/clifford/fix906	Clifford Wolf	2019-03-30	1	-0/+2
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\| * \|	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906	Clifford Wolf	2019-03-29	1	-0/+2
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* \|	Merge pull request #901 from trcwm/libertyfixes	Clifford Wolf	2019-03-28	4	-9/+151
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\| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-1/+1
\| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-1/+1
\| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	4	-9/+151
* \| \|	Merge pull request #903 from YosysHQ/bram_reset_transp	Clifford Wolf	2019-03-28	1	-0/+1
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\| * \|	memory_bram: Reset make_transp when growing read ports	David Shah	2019-03-27	1	-0/+1
* \| \|	Add "read -verific" and "read -noverific"	Clifford Wolf	2019-03-27	1	-6/+28
* \| \|	Add "rename -output"	Clifford Wolf	2019-03-27	1	-3/+23
* \| \|	Improve "rename" help message	Clifford Wolf	2019-03-27	1	-0/+6
* \| \|	Add "cutpoint -undef"	Clifford Wolf	2019-03-26	1	-10/+14
* \| \|	Add "hdlname" attribute	Clifford Wolf	2019-03-26	2	-0/+5
* \| \|	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	2	-15/+93
* \| \|	Add "cutpoint" pass	Clifford Wolf	2019-03-25	2	-0/+165
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* \|	Merge pull request #896 from YosysHQ/transp_fixes	Clifford Wolf	2019-03-25	1	-9/+16
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\| * \|	memory_bram: Fix multiclock make_transp	David Shah	2019-03-24	1	-9/+16
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* \|	Merge pull request #897 from trcwm/libertyfixes	Clifford Wolf	2019-03-25	8	-22/+645
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\| *	spaces -> tabs	Niels Moseley	2019-03-25	1	-78/+78
\| *	EOL is now accepted as ';' replacement on lines that look like: feature_xyz(o...	Niels Moseley	2019-03-25	1	-4/+3
\| *	Updated the liberty parser to accept [A:B] ranges (AST has not been updated)....	Niels Moseley	2019-03-24	8	-7/+631
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*	Add "mutate -none -mode", "mutate -mode none"	Clifford Wolf	2019-03-23	1	-1/+30
*	Add "mutate -s <filename>"	Clifford Wolf	2019-03-23	1	-2/+24
*	Merge pull request #893 from YosysHQ/clifford/btormeminit	Clifford Wolf	2019-03-23	3	-3/+63
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\| *	Add support for memory initialization to write_btor	Clifford Wolf	2019-03-23	1	-0/+53
\| *	Fix BTOR output tags syntax in writye_btor	Clifford Wolf	2019-03-23	1	-2/+1
\| *	Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals	Clifford Wolf	2019-03-23	2	-1/+9
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*	Merge pull request #889 from YosysHQ/clifford/fix888	Clifford Wolf	2019-03-22	1	-1/+10
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\| *	Fix mem2reg handling of memories with upto data ports, fixes #888	Clifford Wolf	2019-03-21	1	-1/+10
* \|	Merge pull request #890 from YosysHQ/clifford/fix887	Clifford Wolf	2019-03-22	1	-1/+26
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\| * \|	Trim init attributes when resizing FFs in "wreduce", fixes #887	Clifford Wolf	2019-03-22	1	-1/+26
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* \|	Merge pull request #891 from YosysHQ/xilinx_keep	David Shah	2019-03-22	2	-25/+31
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\| *	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
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*	Improve "read_verilog -dump_vlog[12]" handling of upto ranges	Clifford Wolf	2019-03-21	1	-3/+6
*	Improve read_verilog debug output capabilities	Clifford Wolf	2019-03-21	3	-15/+42
*	Merge pull request #885 from YosysHQ/clifford/fix873	Clifford Wolf	2019-03-19	1	-2/+4
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\| *	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
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*	Merge pull request #808 from eddiehung/read_aiger	Eddie Hung	2019-03-19	35	-6/+632
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\| *	Merge https://github.com/YosysHQ/yosys into read_aiger	Eddie Hung	2019-03-19	113	-792/+6364
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* \|	Merge pull request #884 from zachjs/master	Clifford Wolf	2019-03-19	2	-1/+61
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\| * \|	fix local name resolution in prefix constructs	Zachary Snow	2019-03-18	2	-1/+61
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* \|	Update issue template	Clifford Wolf	2019-03-17	1	-5/+5
* \|	Update issue template	Clifford Wolf	2019-03-17	1	-0/+8
* \|	Merge pull request #877 from FelixVi/master	Clifford Wolf	2019-03-16	1	-1/+4
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\| * \|	Add note about test requirements in README	Felix Vietmeyer	2019-03-16	1	-1/+4
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* \|	Improve mix of src/wire/wirebit coverage in "mutate -list"	Clifford Wolf	2019-03-16	1	-29/+84