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* | efinix: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-184-102/+164
* | anlogic: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-303/+585
* | ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-514/+293
* | xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1840-2315/+4540
* | gowin: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-266/+576
* | nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1811-519/+679
* | ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-1810-601/+602
* | Add memory_libmap pass.Marcelina Kościelnicka2022-05-186-0/+3884
* | proc_rom: Add special handling of const-0 address bits.Marcelina Kościelnicka2022-05-182-15/+186
* | Bump versiongithub-actions[bot]2022-05-181-1/+1
* | Merge pull request #3310 from robinsonb5-PRs/masterMiodrag Milanović2022-05-171-0/+2
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| * | Use log_warning when Tcl_Init fails, report error with Tcl_ErrnoMsg.Alastair M. Robinson2022-05-161-1/+1
| * | Now calls Tcl_Init after creating the interp, fixes clock format.Alastair M. Robinson2022-05-101-0/+2
* | | opt_ffinv: Use ModIndex instead of ModWalker.Marcelina Kościelnicka2022-05-171-50/+53
* | | Merge pull request #3314 from jix/sva_value_change_logic_wideJannis Harder2022-05-163-9/+72
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| * | | verific: Use new value change logic also for $stable of wide signals.Jannis Harder2022-05-113-9/+72
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* | | Bump versiongithub-actions[bot]2022-05-141-1/+1
* | | Add opt_ffinv pass.Marcelina Kościelnicka2022-05-134-3/+268
* | | Bump versiongithub-actions[bot]2022-05-131-1/+1
* | | Add proc_rom pass.Marcelina Kościelnicka2022-05-135-1/+283
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* | Bump versiongithub-actions[bot]2022-05-101-1/+1
* | Merge pull request #3305 from jix/sva_value_change_logicJannis Harder2022-05-098-11/+121
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| * | verific: Improve logic generated for SVA value change expressionsJannis Harder2022-05-098-11/+121
* | | Merge pull request #3297 from jix/sva_nested_clk_elseJannis Harder2022-05-094-5/+27
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| * | | verific: Fix conditions of SVAs with explicit clocks within proceduresJannis Harder2022-05-034-5/+27
* | | | Next dev cycleMiodrag Milanovic2022-05-092-2/+5
* | | | Release version 0.17Miodrag Milanovic2022-05-092-3/+3
* | | | Update CHANGELOGMiodrag Milanovic2022-05-091-0/+3
* | | | Update manualMiodrag Milanovic2022-05-091-0/+44
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* | | Merge pull request #3299 from YosysHQ/mmicko/sim_memoryMiodrag Milanović2022-05-094-3/+59
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| * | | Handle possible non-memory indexed dataMiodrag Milanovic2022-05-061-8/+10
| * | | map memory location to wire value, if memory is converted to FFsMiodrag Milanovic2022-05-041-0/+4
| * | | fix crash when no fst inputMiodrag Milanovic2022-05-041-1/+2
| * | | Start restoring memory state from VCD/FSTMiodrag Milanovic2022-05-043-3/+50
| * | | Add propagated clock signals into btor info fileClaire Xenia Wolf2022-05-041-0/+2
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* | | Fix running sva testsMiodrag Milanovic2022-05-091-4/+3
* | | Bump versiongithub-actions[bot]2022-05-081-1/+1
* | | opt_mem: Remove constant-value bit lanes.Marcelina Kościelnicka2022-05-073-28/+145
* | | Bump versiongithub-actions[bot]2022-05-071-1/+1
* | | include latest abc changesMiodrag Milanovic2022-05-061-1/+1
* | | include latest abc changesMiodrag Milanovic2022-05-061-1/+1
* | | Merge pull request #3300 from imhcyx/masterMiodrag Milanović2022-05-061-1/+1
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| * | | memory_share: fix wrong argidx in extra_argsimhcyx2022-05-051-1/+1
* | | | Include abc change to fix FreeBSD buildMiodrag Milanovic2022-05-061-1/+1
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* | | Bump versiongithub-actions[bot]2022-05-051-1/+1
* | | abc: Use dict/pool instead of std::map/std::setMarcelina Kościelnicka2022-05-041-14/+14
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* | Bump versiongithub-actions[bot]2022-05-031-1/+1
* | AIM file could have gaps in or between inputs and initsMiodrag Milanovic2022-05-021-3/+6
* | Bump versiongithub-actions[bot]2022-04-301-1/+1
* | Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ffMiodrag Milanović2022-04-291-0/+1
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