aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Fix spacingEddie Hung2019-07-121-1/+1
|
* Remove double pushEddie Hung2019-07-121-1/+0
|
* Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
|
* ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
|
* Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
|
* _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
|
* Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
|
* Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
|\ | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| * synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
| |
* | Merge pull request #1185 from koriakin/xc-ff-init-valsEddie Hung2019-07-112-6/+6
|\ \ | | | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ | | | | | | ISE/Vivado.
* / Enable &mfs for abc9, even if it only currently works for ice40Eddie Hung2019-07-111-1/+1
|/
* Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
|\ | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
* | Merge pull request #1179 from whitequark/attrmap-procClifford Wolf2019-07-111-0/+19
|\ \ | | | | | | attrmap: also consider process, switch and case attributes
| * | attrmap: also consider process, switch and case attributes.whitequark2019-07-101-0/+19
| | |
* | | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
|\ \ \ | | | | | | | | Error out if -abc9 and -retime specified
| * | | Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
| |/ /
* | | Merge pull request #1148 from YosysHQ/xc7muxEddie Hung2019-07-107-49/+415
|\ \ \ | | | | | | | | synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
| * | | Add some spacingEddie Hung2019-07-101-9/+9
| | | |
| * | | Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
| | | |
| * | | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
| | | |
| * | | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
| | | |
| * | | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
| | | |
| * | | Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
| | | |
| * | | Merge remote-tracking branch 'origin/eddie/fix1173' into xc7muxEddie Hung2019-07-092-4/+9
| |\ \ \
| * | | | Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
| | | | |
| * | | | Fix typo and commentsEddie Hung2019-07-091-4/+4
| | | | |
| * | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-0916-79/+348
| |\ \ \ \ | | | |_|/ | | |/| |
| * | | | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
| | | | |
| * | | | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| | | | | | | | | | | | | | | | | | | | This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.
| * | | | Fix spacingEddie Hung2019-07-091-1/+1
| | | | |
| * | | | Fix spacingEddie Hung2019-07-091-1/+1
| | | | |
| * | | | Decompose mux inputs in delay-orientated (rather than area) fashionEddie Hung2019-07-081-18/+30
| | | | |
| * | | | Do not call opt -mux_undef (part of -full) before muxcoverEddie Hung2019-07-081-1/+5
| | | | |
| * | | | Add one more commentEddie Hung2019-07-081-0/+3
| | | | |
| * | | | Less thinkingEddie Hung2019-07-081-3/+3
| | | | |
| * | | | RewordEddie Hung2019-07-081-2/+2
| | | | |
| * | | | synth_xilinx to call "synth -run coarse" with "-keepdc"Eddie Hung2019-07-081-2/+2
| | | | |
| * | | | Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7muxEddie Hung2019-07-084-8/+25
| |\ \ \ \
| * | | | | Map $__XILINX_SHIFTX in a more balanced mannerEddie Hung2019-07-081-36/+49
| | | | | |
| * | | | | CapitalisationEddie Hung2019-07-081-1/+1
| | | | | |
| * | | | | Add synth_xilinx -widemux recommended valueEddie Hung2019-07-081-1/+1
| | | | | |
| * | | | | Fixes for 2:1 muxesEddie Hung2019-07-082-5/+30
| | | | | |
| * | | | | synth_xilinx -widemux=2 is minimum nowEddie Hung2019-07-081-4/+7
| | | | | |
| * | | | | Parametric muxcover costs as per @daveshah1Eddie Hung2019-07-081-16/+14
| | | | | |
| * | | | | Merge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7muxEddie Hung2019-07-081-5/+11
| |\ \ \ \ \
| * | | | | | atoi -> stoi as per @daveshah1Eddie Hung2019-07-081-1/+1
| | | | | | |
| * | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-088-90/+60
| |\ \ \ \ \ \
| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-024-3/+27
| |\ \ \ \ \ \ \
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 22:26:42 +0000