Merge remote-tracking branch 'origin/master' into xc7mux

8 files changed, 60 insertions, 90 deletions

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index eb3d47569..869b741a6 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -138,6 +138,7 @@ struct XAigerWriter
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
+		pool<SigBit> keep_bits;
 
 		// promote public wires
 		for (auto wire : module->wires())
@@ -168,6 +169,9 @@ struct XAigerWriter
 					unused_bits.insert(bit);
 				}
 
+				if (keep)
+					keep_bits.insert(bit);
+
 				if (wire->port_input || keep) {
 					if (bit != wirebit)
 						alias_map[bit] = wirebit;
@@ -235,7 +239,7 @@ struct XAigerWriter
 			log_assert(!holes_mode);
 
 			RTLIL::Module* inst_module = module->design->module(cell->type);
-		    if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
+			if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
 				abc_box_seen = true;
 
 				if (!holes_mode) {
@@ -255,10 +259,11 @@ struct XAigerWriter
 				}
 			}
 			else {
+				bool cell_known = cell->known();
 				for (const auto &c : cell->connections()) {
 					if (c.second.is_fully_const()) continue;
-					auto is_input = cell->input(c.first);
-					auto is_output = cell->output(c.first);
+					auto is_input = !cell_known || cell->input(c.first);
+					auto is_output = !cell_known || cell->output(c.first);
 					if (!is_input && !is_output)
 						log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
 
@@ -266,12 +271,15 @@ struct XAigerWriter
 						for (auto b : c.second.bits()) {
 							Wire *w = b.wire;
 							if (!w) continue;
-							if (!w->port_output) {
+							if (!w->port_output || !cell_known) {
 								SigBit I = sigmap(b);
 								if (I != b)
 									alias_map[b] = I;
 								output_bits.insert(b);
 								unused_bits.erase(b);
+
+								if (!cell_known)
+									keep_bits.insert(b);
 							}
 						}
 					}
@@ -424,7 +432,7 @@ struct XAigerWriter
 
 							auto jt = input_bits.find(b);
 							if (jt != input_bits.end()) {
-								log_assert(b.wire->attributes.count("\\keep"));
+								log_assert(keep_bits.count(O));
 								input_bits.erase(b);
 							}
 						}
@@ -444,7 +452,7 @@ struct XAigerWriter
 			// with $inout.out suffix, make it a PO driven by the existing inout, and
 			// inherit existing inout's drivers
 			if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
-					|| wire->attributes.count("\\keep")) {
+					|| keep_bits.count(bit)) {
 				RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
 				RTLIL::Wire *new_wire = module->wire(wire_name);
 				if (!new_wire)
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d89b2dc88..0fec445fa 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1021,13 +1021,8 @@ list_of_specparam_assignments:
 specparam_assignment:
 	ignspec_id '=' constant_mintypmax_expression ;
 
-/*
-pulsestyle_declaration :
-	;
-
-showcancelled_declaration :
-	;
-*/
+ignspec_opt_cond:
+	TOK_IF '(' ignspec_expr ')' | /* empty */;
 
 path_declaration :
 	simple_path_declaration ';'
@@ -1036,8 +1031,8 @@ path_declaration :
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value |
-	full_path_description '=' path_delay_value
+	ignspec_opt_cond parallel_path_description '=' path_delay_value |
+	ignspec_opt_cond full_path_description '=' path_delay_value
 	;
 
 path_delay_value :
@@ -1047,32 +1042,20 @@ path_delay_value :
 	;
 
 list_of_path_delay_extra_expressions :
-/*
-	t_path_delay_expression
-	| trise_path_delay_expression ',' tfall_path_delay_expression
-	| trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression
-	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
-	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
-	  t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
-	  tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
-*/
-	',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	;
+	',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
+
+specify_edge_identifier :
+	TOK_POSEDGE | TOK_NEGEDGE ;
 
 parallel_path_description :
-	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
+	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 full_path_description :
-	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
+	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 // This was broken into 2 rules to solve shift/reduce conflicts
 list_of_path_inputs :
@@ -1112,56 +1095,6 @@ system_timing_args :
 	system_timing_arg |
 	system_timing_args ',' system_timing_arg ;
 
-/*
-t_path_delay_expression :
-	path_delay_expression;
-
-trise_path_delay_expression :
-	path_delay_expression;
-
-tfall_path_delay_expression :
-	path_delay_expression;
-
-tz_path_delay_expression :
-	path_delay_expression;
-
-t01_path_delay_expression :
-	path_delay_expression;
-
-t10_path_delay_expression :
-	path_delay_expression;
-
-t0z_path_delay_expression :
-	path_delay_expression;
-
-tz1_path_delay_expression :
-	path_delay_expression;
-
-t1z_path_delay_expression :
-	path_delay_expression;
-
-tz0_path_delay_expression :
-	path_delay_expression;
-
-t0x_path_delay_expression :
-	path_delay_expression;
-
-tx1_path_delay_expression :
-	path_delay_expression;
-
-t1x_path_delay_expression :
-	path_delay_expression;
-
-tx0_path_delay_expression :
-	path_delay_expression;
-
-txz_path_delay_expression :
-	path_delay_expression;
-
-tzx_path_delay_expression :
-	path_delay_expression;
-*/
-
 path_delay_expression :
 	ignspec_constant_expression;
 
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 1a25c477f..3009bf2c0 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}.
 An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and
 exactly one RTLIL::CaseRule object, which is called the {\it root case}.
 
-An RTLIL::SyncRule object contains an (optional) synchronization condition
-(signal and edge-type) and zero or more assignments (RTLIL::SigSig).
+An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or
+more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial
+loops when a latch should be inferred instead.
 
 An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
 and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a
diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 9e5727499..66d661fa1 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -779,6 +779,9 @@ class WClass:
 
 			#if self.link_type != link_types.pointer:
 			text += "\n\t\tstatic " + self.name + "* get_py_obj(" + long_name + "* ref)\n\t\t{"
+			text += "\n\t\t\tif(ref == nullptr){"
+			text += "\n\t\t\t\tthrow std::runtime_error(\"" + self.name + " does not exist.\");"
+			text += "\n\t\t\t}"
 			text += "\n\t\t\t" + self.name + "* ret = (" + self.name + "*)malloc(sizeof(" + self.name + "));"
 			if self.link_type == link_types.pointer:
 				text += "\n\t\t\tret->ref_obj = ref;"
diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index 8271cd249..a08b613a8 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -3,3 +3,7 @@ initial o = 1'b0;
 always @*
     o <= ~o;
 endmodule
+
+module abc9_test028(input i, output o);
+unknown u(~i, o);
+endmodule
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 922f7005d..a84b637d9 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -1,4 +1,6 @@
 read_verilog abc9.v
+design -save read
+hierarchy -top abc9_test027
 proc
 design -save gold
 
@@ -12,3 +14,11 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+design -load read
+hierarchy -top abc9_test028
+proc
+
+abc9 -lut 4
+select -assert-count 1 t:$lut r:LUT=1 r:WIDTH=1 %i %i
+select -assert-count 1 t:unknown
+select -assert-none t:$lut t:unknown %% t: %D
diff --git a/tests/various/specify.v b/tests/various/specify.v
index afc421da8..5d44d78f7 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,9 +7,11 @@ module test (
 		if (EN) Q <= D;
 
 	specify
-		if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
+		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
 		$setup(D, posedge CLK &&& EN, 5);
 		$hold(posedge CLK, D &&& EN, 6);
+`endif
 	endspecify
 endmodule
 
@@ -28,3 +30,10 @@ module test2 (
 		(B => Q) = 1.5;
 	endspecify
 endmodule
+
+module issue01144(input clk, d, output q);
+specify
+  (posedge clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a5ca07219..00597e1e2 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -54,3 +54,5 @@ equiv_struct
 equiv_induct -seq 5
 equiv_status -assert
 design -reset
+
+read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v