Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
|\ | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)" | ||||
| * | Revert "Recognise default entry in case even if all cases covered (fix for ↵ | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
|/ | | | | #931)" | ||||
* | Merge pull request #936 from YosysHQ/README-fix-quotes | Eddie Hung | 2019-04-15 | 1 | -2/+2 |
|\ | | | | | README: fix some incorrect quoting | ||||
| * | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 |
|/ | |||||
* | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 |
|\ | | | | | Add additional cells sim models for core 7-series primitives. | ||||
| * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 |
| | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 |
| | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 |
| | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
* | | Merge pull request #933 from dh73/master | Clifford Wolf | 2019-04-12 | 1 | -3/+9 |
|\ \ | | | | | | | Fixing issues in CycloneV cell sim | ||||
| * | | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 |
| |/ | |||||
* | | Merge pull request #932 from YosysHQ/eddie/fixdlatch | Clifford Wolf | 2019-04-12 | 2 | -3/+4 |
|\ \ | |/ |/| | Recognise default entry in case even if all cases covered (fix for #931) | ||||
| * | Add default entry to testcase | Eddie Hung | 2019-04-11 | 1 | -2/+3 |
| | | |||||
| * | Recognise default entry in case even if all cases covered (#931) | Eddie Hung | 2019-04-11 | 1 | -1/+1 |
|/ | |||||
* | Fix a few typos | Eddie Hung | 2019-04-08 | 1 | -3/+3 |
| | |||||
* | Merge pull request #919 from YosysHQ/multiport_transp | Clifford Wolf | 2019-04-08 | 1 | -1/+2 |
|\ | | | | | memory_bram: Fix multiport make_transp | ||||
| * | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 5 | -3/+39 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Added missing argument checking to "mutate" command | Clifford Wolf | 2019-04-04 | 1 | -0/+32 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #913 from smunaut/fix_proc_mux | Eddie Hung | 2019-04-03 | 1 | -1/+1 |
|\ | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | ||||
| * | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | Sylvain Munaut | 2019-04-03 | 1 | -1/+1 |
|/ | | | | | | last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | Merge pull request #912 from YosysHQ/bram_addr_en | Clifford Wolf | 2019-04-03 | 1 | -0/+2 |
|\ | | | | | memory_bram: Consider read enable for address expansion register | ||||
| * | memory_bram: Consider read enable for address expansion register | David Shah | 2019-04-02 | 1 | -0/+2 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Merge pull request #910 from ucb-bar/memupdates | Clifford Wolf | 2019-04-03 | 1 | -30/+173 |
|\ \ | |/ |/| | Refine memory support to deal with general Verilog memory definitions. | ||||
| * | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 |
| | | |||||
* | | Merge pull request #895 from YosysHQ/pmux2shiftx | Eddie Hung | 2019-04-02 | 1 | -0/+28 |
|\ \ | |/ |/| | RFC: Add a pmux-to-shiftx optimisation to proc_mux | ||||
| * | Create one $shiftx per bit in width | Eddie Hung | 2019-03-25 | 1 | -10/+17 |
| | | |||||
| * | Add a pmux-to-shiftx optimisation to proc_mux | Eddie Hung | 2019-03-23 | 1 | -0/+21 |
| | | |||||
* | | Merge pull request #907 from YosysHQ/clifford/fix906 | Clifford Wolf | 2019-03-30 | 1 | -0/+2 |
|\ \ | | | | | | | Build Verilog parser with -DYYMAXDEPTH=100000 | ||||
| * | | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 |
|/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge pull request #901 from trcwm/libertyfixes | Clifford Wolf | 2019-03-28 | 4 | -9/+151 |
|\ \ | | | | | | | Libertyfixes: accept superfluous ; at end of group. | ||||
| * | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 1 | -1/+1 |
| | | | |||||
| * | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 1 | -1/+1 |
| | | | |||||
| * | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 4 | -9/+151 |
| | | | |||||
* | | | Merge pull request #903 from YosysHQ/bram_reset_transp | Clifford Wolf | 2019-03-28 | 1 | -0/+1 |
|\ \ \ | |/ / |/| | | memory_bram: Reset make_transp when growing read ports | ||||
| * | | memory_bram: Reset make_transp when growing read ports | David Shah | 2019-03-27 | 1 | -0/+1 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | Add "read -verific" and "read -noverific" | Clifford Wolf | 2019-03-27 | 1 | -6/+28 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Add "rename -output" | Clifford Wolf | 2019-03-27 | 1 | -3/+23 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Improve "rename" help message | Clifford Wolf | 2019-03-27 | 1 | -0/+6 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Add "cutpoint -undef" | Clifford Wolf | 2019-03-26 | 1 | -10/+14 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Add "hdlname" attribute | Clifford Wolf | 2019-03-26 | 2 | -0/+5 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 2 | -15/+93 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Add "cutpoint" pass | Clifford Wolf | 2019-03-25 | 2 | -0/+165 |
|/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge pull request #896 from YosysHQ/transp_fixes | Clifford Wolf | 2019-03-25 | 1 | -9/+16 |
|\ \ | | | | | | | memory_bram: Fix multiclock make_transp | ||||
| * | | memory_bram: Fix multiclock make_transp | David Shah | 2019-03-24 | 1 | -9/+16 |
| |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Merge pull request #897 from trcwm/libertyfixes | Clifford Wolf | 2019-03-25 | 8 | -22/+645 |
|\ \ | |/ |/| | Liberty parser: Accept ranges [A:B], and ignore missing ';'. | ||||
| * | spaces -> tabs | Niels Moseley | 2019-03-25 | 1 | -78/+78 |
| | | |||||
| * | EOL is now accepted as ';' replacement on lines that look like: ↵ | Niels Moseley | 2019-03-25 | 1 | -4/+3 |
| | | | | | | | | feature_xyz(option) | ||||
| * | Updated the liberty parser to accept [A:B] ranges (AST has not been ↵ | Niels Moseley | 2019-03-24 | 8 | -7/+631 |
|/ | | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'. | ||||
* | Add "mutate -none -mode", "mutate -mode none" | Clifford Wolf | 2019-03-23 | 1 | -1/+30 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "mutate -s <filename>" | Clifford Wolf | 2019-03-23 | 1 | -2/+24 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> |