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| * | Improved cells_sim_digital model for GP_COUNT8Andrew Zonenberg2017-08-142-40/+75
| * | Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digitalAndrew Zonenberg2017-08-144-428/+451
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* | Merge pull request #383 from azonenberg/abcfnamesClifford Wolf2017-08-141-0/+3
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| * | abc: Allow +/ filenames in the abc commandRobert Ou2017-08-141-0/+3
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* | Merge pull request #382 from azonenberg/jsoniofixClifford Wolf2017-08-141-0/+1
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| * | json: Parse inout correctly rather than as an outputRobert Ou2017-08-141-0/+1
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* | Merge pull request #384 from azonenberg/crtechlibClifford Wolf2017-08-141-2/+66
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| * coolrunner2: Add INVERT parameter to some BUFGsRobert Ou2017-08-141-2/+6
| * coolrunner2: Add FFs with clock enable to cells_sim.vRobert Ou2017-08-141-0/+60
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* Add support for set-reset cell variants to opt_rmdffClifford Wolf2017-08-091-0/+182
* Auto-detect JSON front-endClifford Wolf2017-08-091-0/+2
* Add handling of constant reset signals to opt_rmdffClifford Wolf2017-08-061-1/+23
* Add "yosys-smtbmc --smtc-init --smtc-top --noinit"Clifford Wolf2017-08-041-20/+66
* Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags"Clifford Wolf2017-08-041-1/+5
* Fix typo in "abc" pass help messageClifford Wolf2017-07-291-1/+1
* Add merging of "past FFs" to verific importerClifford Wolf2017-07-291-2/+76
* Add consolidation of init attributes to opt_clean, some opt_clean log fixesClifford Wolf2017-07-291-6/+82
* Add minimal support for PSL in VHDL via VerificClifford Wolf2017-07-281-19/+155
* Add simple VHDL+PSL exampleClifford Wolf2017-07-284-17/+64
* Improve Verific HDL language optionsClifford Wolf2017-07-281-4/+4
* Fix handling of non-user-declared Verific netbusClifford Wolf2017-07-281-2/+3
* Improve Verific SVA importerClifford Wolf2017-07-272-7/+42
* Add counter.sv SVA testClifford Wolf2017-07-271-0/+29
* Add log_warning_noprefix() API, Use for Verific warnings and errorsClifford Wolf2017-07-273-1/+37
* Add "verific -import -n" and "verific -import -nosva"Clifford Wolf2017-07-271-14/+36
* Improve SVA tests, add Makefile and scriptsClifford Wolf2017-07-2711-9/+110
* Improve Verific SVA import: negedge and $pastClifford Wolf2017-07-271-6/+49
* Improve Verific SVA importerClifford Wolf2017-07-271-37/+58
* Add "opt_expr -fine" feature to remove neutral bits from reduce and logic ope...Clifford Wolf2017-07-261-0/+47
* Improve Verific bindings (mostly related to SVA)Clifford Wolf2017-07-261-110/+320
* Improve "help verific" messageClifford Wolf2017-07-251-5/+5
* Add "verific -extnets"Clifford Wolf2017-07-251-23/+130
* Add "using std::get" to yosys.hClifford Wolf2017-07-251-0/+1
* Improve "verific -all" handlingClifford Wolf2017-07-251-26/+45
* Add "verific -import -d <dump_file"Clifford Wolf2017-07-241-6/+35
* Add "verific -import -flatten" and "verific -import -v"Clifford Wolf2017-07-241-107/+164
* Add more SVA test cases for future Verific workClifford Wolf2017-07-225-1/+74
* Add "verific -import -k"Clifford Wolf2017-07-221-42/+51
* Add error for cell output ports that are connected to constantsClifford Wolf2017-07-221-20/+21
* Add some simple SVA test cases for future Verific workClifford Wolf2017-07-224-0/+45
* Improve docs for verific bindings, add simply sby exampleClifford Wolf2017-07-225-48/+89
* Fix handling of empty cell port assignments (i.e. ignore them)Clifford Wolf2017-07-212-0/+6
* Fix "read_blif -wideports" handling of cells with wide portsClifford Wolf2017-07-211-3/+33
* Add a paragraph about pre-defined macros to read_verilog help messageClifford Wolf2017-07-211-0/+4
* Add verilator support to testbenches generated by yosys-smtbmcClifford Wolf2017-07-211-3/+15
* Change intptr_t to uintptr_t in hashlib.hClifford Wolf2017-07-181-1/+1
* Merge pull request #363 from rqou/masterClifford Wolf2017-07-182-1/+6
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| * makefile: Add the option to use libtermcapRobert Ou2017-07-171-0/+5
| * Fix build warnings for win64Robert Ou2017-07-171-1/+1
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* Add $alu to list of supported cells for "stat -width"Clifford Wolf2017-07-141-1/+1