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| author | Clifford Wolf <clifford@clifford.at> | 2017-08-06 13:27:18 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-06 13:27:18 +0200 |
| commit | c4a7958f70be956130119bbb3c682df8e0953b9c (patch) | |
| tree | 4c9a1fb3555eb086aaca2366ffd49d30099756e9 | |
| parent | 48b2b376d0c2bf1f8e32b2f201923783c65108f0 (diff) | |
| download | yosys-c4a7958f70be956130119bbb3c682df8e0953b9c.tar.gz yosys-c4a7958f70be956130119bbb3c682df8e0953b9c.tar.bz2 yosys-c4a7958f70be956130119bbb3c682df8e0953b9c.zip | |
Add handling of constant reset signals to opt_rmdff
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 0eefd6a86..80217464c 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -186,7 +186,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) goto delete_dff; } - if (sig_d == sig_q && (!sig_r.size() || !has_init || val_init == val_rv)) { + if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) { if (sig_r.size()) mod->connect(sig_q, val_rv); if (has_init) @@ -194,6 +194,28 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) goto delete_dff; } + if (!sig_r.empty() && sig_r.is_fully_const()) + { + if (sig_r == val_rp || sig_r.is_fully_undef()) { + mod->connect(sig_q, val_rv); + goto delete_dff; + } + + log("Removing unused reset from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); + + if (dff->type == "$adff") { + dff->type = "$dff"; + dff->unsetPort("\\ARST"); + dff->unsetParam("\\ARST_POLARITY"); + dff->unsetParam("\\ARST_VALUE"); + return true; + } + + log_assert(dff->type.substr(0,6) == "$_DFF_"); + dff->type = stringf("$_DFF_%c_", + dff->type[6]); + dff->unsetPort("\\R"); + } + return false; delete_dff: |