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| author | Robert Ou <rqou@robertou.com> | 2017-08-01 11:58:01 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 12:13:25 -0700 |
| commit | 1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57 (patch) | |
| tree | 7180ae460b5518a73025fb8ecb7a8b8a0b0d6394 | |
| parent | 007f29b9c221ab1a8931de863517d6990218970d (diff) | |
| download | yosys-1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57.tar.gz yosys-1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57.tar.bz2 yosys-1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57.zip | |
coolrunner2: Add FFs with clock enable to cells_sim.v
| -rw-r--r-- | techlibs/coolrunner2/cells_sim.v | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v index e08ee5f9b..d8dca1922 100644 --- a/techlibs/coolrunner2/cells_sim.v +++ b/techlibs/coolrunner2/cells_sim.v @@ -244,3 +244,63 @@ module FTDCP (C, PRE, CLR, T, Q); assign Q = Q_; endmodule + +module FDCPE (C, PRE, CLR, D, Q, CE); + parameter INIT = 0; + + input C, PRE, CLR, D, CE; + output reg Q; + + initial begin + Q <= INIT; + end + + always @(posedge C, posedge PRE, posedge CLR) begin + if (CLR == 1) + Q <= 0; + else if (PRE == 1) + Q <= 1; + else if (CE == 1) + Q <= D; + end +endmodule + +module FDCPE_N (C, PRE, CLR, D, Q, CE); + parameter INIT = 0; + + input C, PRE, CLR, D, CE; + output reg Q; + + initial begin + Q <= INIT; + end + + always @(negedge C, posedge PRE, posedge CLR) begin + if (CLR == 1) + Q <= 0; + else if (PRE == 1) + Q <= 1; + else if (CE == 1) + Q <= D; + end +endmodule + +module FDDCPE (C, PRE, CLR, D, Q, CE); + parameter INIT = 0; + + input C, PRE, CLR, D, CE; + output reg Q; + + initial begin + Q <= INIT; + end + + always @(posedge C, negedge C, posedge PRE, posedge CLR) begin + if (CLR == 1) + Q <= 0; + else if (PRE == 1) + Q <= 1; + else if (CE == 1) + Q <= D; + end +endmodule |