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* corrected abstract of appnoteAhmed Irfan2014-11-031-5/+5
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* removed unused bibAhmed Irfan2014-11-031-12/+12
| | | | removed unused bibitems from the appnote verilog to btor
* corrections in appnoteAhmed Irfan2014-11-031-1/+2
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* appnote addedAhmed Irfan2014-11-031-0/+434
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-22513-12050/+34829
|\ | | | | | | | | | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
| * Re-enabled assert for new logic loops in "share" passClifford Wolf2014-09-211-4/+1
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| * Various improvements regarding logic loops in "share" resultsClifford Wolf2014-09-211-37/+108
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| * Logic loop bugfix for "share" passClifford Wolf2014-09-211-3/+7
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| * Added "share -limit"Clifford Wolf2014-09-211-1/+13
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| * Still loop bug in "share": changed assert to warningClifford Wolf2014-09-211-13/+25
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| * Do not introduce new logic loops in "share"Clifford Wolf2014-09-211-6/+47
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| * Assert on new logic loops in "share" passClifford Wolf2014-09-212-1/+49
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| * Added "test_abcloop" commandClifford Wolf2014-09-192-0/+286
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| * Initialize RTLIL::Const from std::vector<bool>Clifford Wolf2014-09-192-1/+9
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| * Sorting of object names in ilang backendClifford Wolf2014-09-192-21/+49
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| * Small improvements in "abc" command handle_loops() functionClifford Wolf2014-09-191-6/+9
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| * Using "NOT" instead of "INV" as cell name in default abc genlib fileClifford Wolf2014-09-191-2/+2
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| * Alphabetically sort port names in "show" outputClifford Wolf2014-09-191-0/+3
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| * Do not run "scorr" in "abc -fast"Clifford Wolf2014-09-181-4/+4
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| * Improvements in "synth" scriptClifford Wolf2014-09-181-8/+12
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| * Added "abc -fast"Clifford Wolf2014-09-181-6/+31
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| * Added commit count to devel version numberClifford Wolf2014-09-171-1/+1
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| * Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-161-1/+1
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| * Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-161-4/+6
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| * Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)Clifford Wolf2014-09-163-65/+84
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| * Fixed $macc simlib model for zero-configClifford Wolf2014-09-161-1/+1
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| * More aggressive $macc merging in alumaccClifford Wolf2014-09-151-1/+37
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| * Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-152-0/+61
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| * Improved maccmap tree bit packingClifford Wolf2014-09-151-16/+50
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| * Fixed wreduce $shiftx handlingClifford Wolf2014-09-151-1/+1
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| * Fixed monitor notifications for removed cellClifford Wolf2014-09-141-0/+3
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| * Added "synth" commandClifford Wolf2014-09-146-20/+174
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| * Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-141-9/+16
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| * Using alumacc in techmap.vClifford Wolf2014-09-141-237/+33
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| * Various fixes/cleanups in alumacc and maccmapClifford Wolf2014-09-142-2/+11
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| * Added techmap_wrap attributeClifford Wolf2014-09-141-5/+28
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| * alumacc fix for $pos cellsClifford Wolf2014-09-141-13/+24
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| * Extract $alu cells in alumaccClifford Wolf2014-09-141-1/+296
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| * Merge $macc cells in alumacc passClifford Wolf2014-09-141-1/+59
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| * Basic $macc extract in alumaccClifford Wolf2014-09-141-4/+104
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| * alumacc skeletonClifford Wolf2014-09-142-0/+64
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| * Cleanup in wreduceClifford Wolf2014-09-141-11/+8
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| * Using pkg-config to find libffiClifford Wolf2014-09-131-2/+2
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| * Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
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| * Simplified $fa undef modelClifford Wolf2014-09-083-15/+6
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| * Fixes and cleanups for blackbox.vClifford Wolf2014-09-082-70/+73
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| * Added $lcu cell typeClifford Wolf2014-09-088-76/+142
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| * Another $clog2 bugfixClifford Wolf2014-09-081-0/+2
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| * Added "$fa" cell typeClifford Wolf2014-09-088-6/+165
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| * Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-081-5/+27
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