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author | Clifford Wolf <clifford@clifford.at> | 2014-09-18 12:57:55 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-09-18 12:57:55 +0200 |
commit | 4888d61c651e1230c592cff7c0d8143bcc8394e1 (patch) | |
tree | e4fc069f82765f6f5773282606399bbc15edc8c6 | |
parent | 815fab9d7136506aec0d38300e68bd88810195d3 (diff) | |
download | yosys-4888d61c651e1230c592cff7c0d8143bcc8394e1.tar.gz yosys-4888d61c651e1230c592cff7c0d8143bcc8394e1.tar.bz2 yosys-4888d61c651e1230c592cff7c0d8143bcc8394e1.zip |
Improvements in "synth" script
-rw-r--r-- | techlibs/common/synth.cc | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 95221afa9..4ccacd30b 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -66,18 +66,20 @@ struct SynthPass : public Pass { log(" wreduce\n"); log(" alumacc\n"); log(" share\n"); - log(" opt -fast\n"); + log(" opt\n"); log(" fsm\n"); log(" opt -fast\n"); - log(" memory\n"); + log(" memory -nomap\n"); + log(" opt_clean\n"); log("\n"); log(" fine:\n"); + log(" memory_map\n"); log(" techmap\n"); log(" opt -fast\n"); #ifdef YOSYS_ENABLE_ABC - log(" abc\n"); + log(" abc -fast\n"); + log(" opt_clean\n"); #endif - log(" clean\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) @@ -130,20 +132,22 @@ struct SynthPass : public Pass { Pass::call(design, "wreduce"); Pass::call(design, "alumacc"); Pass::call(design, "share"); - Pass::call(design, "opt -fast"); + Pass::call(design, "opt"); Pass::call(design, "fsm"); Pass::call(design, "opt -fast"); - Pass::call(design, "memory"); + Pass::call(design, "memory -nomap"); + Pass::call(design, "opt_clean"); } if (check_label(active, run_from, run_to, "fine")) { + Pass::call(design, "memory_map"); Pass::call(design, "techmap"); Pass::call(design, "opt -fast"); #ifdef YOSYS_ENABLE_ABC - Pass::call(design, "abc"); + Pass::call(design, "abc -fast"); + Pass::call(design, "opt_clean"); #endif - Pass::call(design, "clean"); } log_pop(); |