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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-19 13:15:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-19 13:15:31 +0200 |
| commit | 3aa003c8e9c207758797e533cb85514cdb0db2c6 (patch) | |
| tree | f45e1fd3e5a002ace3ac9415e70cf32edeb4b247 | |
| parent | f7bb8f244beff135aa2ef6c771bece45ce240c5d (diff) | |
| download | yosys-3aa003c8e9c207758797e533cb85514cdb0db2c6.tar.gz yosys-3aa003c8e9c207758797e533cb85514cdb0db2c6.tar.bz2 yosys-3aa003c8e9c207758797e533cb85514cdb0db2c6.zip | |
Using "NOT" instead of "INV" as cell name in default abc genlib file
| -rw-r--r-- | passes/abc/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index d99eff7d7..75368e3ce 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -712,7 +712,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); fprintf(f, "GATE ONE 1 Y=CONST1;\n"); fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n"); - fprintf(f, "GATE INV 1 Y=!A; PIN * INV 1 999 1 0 1 0\n"); + fprintf(f, "GATE NOT 1 Y=!A; PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE AND 1 Y=A*B; PIN * NONINV 1 999 1 0 1 0\n"); fprintf(f, "GATE NAND 1 Y=!(A*B); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE OR 1 Y=A+B; PIN * NONINV 1 999 1 0 1 0\n"); @@ -854,7 +854,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std module->connect(conn); continue; } - if (c->type == "\\INV") { + if (c->type == "\\NOT") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_"); cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); |