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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-14 17:04:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-14 17:04:39 +0200 |
| commit | 2442eb38327f42e1e786f7dd9ddf1838bf2bf4b4 (patch) | |
| tree | f6b390949823d53d28f113e48ecd2f32a377cd5c | |
| parent | 7815f81c320a025c5b92677e375c12951dcbd14b (diff) | |
| download | yosys-2442eb38327f42e1e786f7dd9ddf1838bf2bf4b4.tar.gz yosys-2442eb38327f42e1e786f7dd9ddf1838bf2bf4b4.tar.bz2 yosys-2442eb38327f42e1e786f7dd9ddf1838bf2bf4b4.zip | |
Fixed monitor notifications for removed cell
| -rw-r--r-- | kernel/rtlil.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ec4375f2f..6556b82ee 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1148,6 +1148,9 @@ void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires) void RTLIL::Module::remove(RTLIL::Cell *cell) { + while (!cell->connections_.empty()) + cell->unsetPort(cell->connections_.begin()->first); + log_assert(cells_.count(cell->name) != 0); log_assert(refcount_cells_ == 0); cells_.erase(cell->name); |