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* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
* kernel/mem: Commit new values of attributes in emit.Marcelina Kościelnicka2021-07-121-0/+4
* kernel/mem: Make the Mem helpers inherit from AttrObject.Marcelina Kościelnicka2021-07-121-8/+4
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-128-25/+62
* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
* Update to latest Verific with extensions for initial assertionsMiodrag Milanovic2021-07-092-15/+10
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-062-2/+11
* ecp5: Add DCSC blackboxgatecat2021-07-061-0/+10
* Merge pull request #2835 from YosysHQ/verific_commandClaire Xen2021-07-051-0/+61
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| * Add additional helpMiodrag Milanovic2021-07-051-0/+22
| * Support command files in VerificMiodrag Milanovic2021-06-161-0/+39
* | Makefile: allow running multiple sanitizers at onceXiretza2021-07-051-3/+3
* | Makefile: use git/make -C instead of cdXiretza2021-07-051-3/+3
* | Makefile: pass PRETTY=0 to ABCXiretza2021-07-051-1/+1
* | Makefile: don't bake DESTDIR into libyosys DT_SONAMEXiretza2021-07-051-2/+2
* | Makefile: clean up PYOSYS configurationXiretza2021-07-051-34/+10
* | Merge pull request #2842 from whitequark/fix-wasi-buildwhitequark2021-06-191-1/+1
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| * | Fix WASI build after commit 1d88bea1.whitequark2021-06-191-1/+1
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* | Merge pull request #2836 from YosysHQ/gatecat/pyosys-sigintMiodrag Milanović2021-06-181-0/+2
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| * | pyosys: Clear SIGINT handler after Python loadsgatecat2021-06-161-0/+2
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* | Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
* | sv: fix up end label checkingZachary Snow2021-06-167-7/+98
* | Include blif reader header in public facing extension header files.Ashton Snelgrove2021-06-161-0/+1
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* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
* macos: fix leak in proc_self_dirname()Zachary Snow2021-06-141-1/+3
* Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-093-122/+120
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09325-1308/+1311
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| * Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| * Intersynth URLClaire Xenia Wolf2021-06-092-2/+2
| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| * Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
| * More deadname stuffClaire Xenia Wolf2021-06-0910-27/+27
| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-0920-26/+26
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-095-422/+422
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-08309-331/+330
| * Add claire deadname stuff to .mailmapClaire Xenia Wolf2021-06-081-0/+4
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-084-13/+41
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-084-5/+94
* | autoname: simple perf optimizationsZachary Snow2021-06-081-11/+15
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* sv: support tasks and functions within packagesZachary Snow2021-06-015-2/+56
* kernel/mem: Recognize some deprecated memory port configs.Marcelina Kościelnicka2021-06-011-0/+10
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