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author | Xiretza <xiretza@xiretza.xyz> | 2021-03-17 00:08:43 +0100 |
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committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-14 13:56:51 -0400 |
commit | 9ca5a91724e114ebb8c04be8edfc0f2f5e8073a9 (patch) | |
tree | c7fe55ad6cbe21dbcfd77693c8e5c368aac5110c | |
parent | b516c681fe6c06fb089fe1e1bc081ffeb56c7949 (diff) | |
download | yosys-9ca5a91724e114ebb8c04be8edfc0f2f5e8073a9.tar.gz yosys-9ca5a91724e114ebb8c04be8edfc0f2f5e8073a9.tar.bz2 yosys-9ca5a91724e114ebb8c04be8edfc0f2f5e8073a9.zip |
ast: fix error condition causing assert to fail
type2str returns a string that doesn't start with $ or \, so it can't be
assigned to an IdString.
-rw-r--r-- | frontends/ast/genrtlil.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 52e057486..6b119b7ff 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -2006,8 +2006,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) default: for (auto f : log_files) current_ast_mod->dumpAst(f, "verilog-ast> "); - type_name = type2str(type); - log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str()); + log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str()); } return RTLIL::SigSpec(); |